From: Luke Kenneth Casson Leighton Date: Sun, 11 Sep 2022 19:30:48 +0000 (+0100) Subject: assembler X-Git-Tag: opf_rfc_ls005_v1~487 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e925df8bfe1233a75c33c7372477ab45b3442eff;p=libreriscv.git assembler --- diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 5ce770f0c..a42df4b2c 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -420,7 +420,7 @@ for other purposes. **{EXT200-263}** bit6=new bit7=scalar -This encoding represents the opportunity to introduce EXT200-263. +This encoding represents the opportunity to introduce EXT200-263. It is a Scalar-word encoding, and does not require implementing SVP64 or SVP64-Single. PO2 is in the range 0b00000 to 0b11111 to represent EXT200-263 respectively. @@ -522,7 +522,7 @@ prohibited either. 293 # after an interrupt, or after the user has updated src/dst step 294 # let's assume the user has prepared src/dst step before running this 295 # vector instruction - 296 def test_intpred_reentrant(self): + 296 # test_intpred_reentrant 297 # reg num 0 1 2 3 4 5 6 7 8 9 10 11 12 298 # srcstep=1 v 299 # src r3=0b0101 Y N Y N @@ -533,7 +533,7 @@ prohibited either. 304 # dest ~r3=0b1010 N Y N Y 305 # dststep=2 ^ 306 - 307 isa = SVP64Asm(['sv.extsb/sm=r3/dm=~r3 *5, *9']) + 307 sv.extsb/sm=r3/dm=~r3 *5, *9 ``` @@ -551,18 +551,16 @@ could then be performed. Full Rationale at ``` - 80 def test_sv_branch_cond_all(self): + 80 # test_sv_branch_cond_all 81 for i in [7, 8, 9]: - 82 lst = SVP64Asm( - 83 [f"addi 1, 0, {i+1}", # set r1 to i - 84 f"addi 2, 0, {i}", # set r2 to i - 85 "cmpi cr0, 1, 1, 8", # compare r1 with 10 and store to cr0 - 86 "cmpi cr1, 1, 2, 8", # compare r2 with 10 and store to cr1 - 87 "sv.bc/all 12, *1, 0xc", # bgt 0xc - branch if BOTH - 88 # r1 AND r2 greater 8 to the nop below - 89 "addi 3, 0, 0x1234", # if tests fail this shouldn't execute - 90 "or 0, 0, 0"] # branch target - 91 ) + 83 addi 1, 0, i+1 # set r1 to i + 84 addi 2, 0, i # set r2 to i + 85 cmpi cr0, 1, 1, 8 # compare r1 with 10 and store to cr0 + 86 cmpi cr1, 1, 2, 8 # compare r2 with 10 and store to cr1 + 87 sv.bc/all 12, *1, 0xc # bgt 0xc - branch if BOTH + 88 # r1 AND r2 greater 8 to the nop below + 89 addi 3, 0, 0x1234, # if tests fail this shouldn't execute + 90 or 0, 0, 0 # branch target ``` @@ -579,18 +577,18 @@ The cosine table may be computed (once) with 18 Vector instructions (one of them `fcos`) ``` -1014 def test_sv_remap_fpmadds_ldbrev_idct_8_mode_4(self): -1015 """>>> lst = [# LOAD bit-reversed with half-swap -1016 "svshape 8, 1, 1, 14, 0", -1017 "svremap 1, 0, 0, 0, 0, 0, 0", -1018 "sv.lfs/els *0, 4(1)", +1014 # test_sv_remap_fpmadds_ldbrev_idct_8_mode_4 +1015 # LOAD bit-reversed with half-swap +1016 svshape 8, 1, 1, 14, 0 +1017 svremap 1, 0, 0, 0, 0, 0, 0 +1018 sv.lfs/els *0, 4(1) 1019 # Outer butterfly, iterative sum -1020 "svremap 31, 0, 1, 2, 1, 0, 1", -1021 "svshape 8, 1, 1, 11, 0", -1022 "sv.fadds *0, *0, *0", +1020 svremap 31, 0, 1, 2, 1, 0, 1 +1021 svshape 8, 1, 1, 11, 0 +1022 sv.fadds *0, *0, *0 1023 # Inner butterfly, twin +/- MUL-ADD-SUB -1024 "svshape 8, 1, 1, 10, 0", -1025 "sv.ffmadds *0, *0, *0, *8" +1024 svshape 8, 1, 1, 10, 0 +1025 sv.ffmadds *0, *0, *0, *8 ``` @@ -604,11 +602,10 @@ repetition of data is required. These 3 instructions may be used as the "inner triple-loop kernel" of the usual 6-loop Massive Matrix Multiply. ``` - 28 def test_sv_remap1(self): - 29 """>>> lst = ["svshape 2, 2, 3, 0, 0", - 30 "svremap 31, 1, 2, 3, 0, 0, 0", - 31 "sv.fmadds *0, *8, *16, *0" - 32 ] + 28 # test_sv_remap1 5x4 by 4x3 matrix multiply + 29 svshape 5, 4, 3, 0, 0 + 30 svremap 31, 1, 2, 3, 0, 0, 0 + 31 sv.fmadds *0, *8, *16, *0 ``` @@ -621,11 +618,11 @@ thus may even usefully be deployed on non-associative and non-commutative operations. ``` - 75 def test_sv_remap2(self): - 76 """>>> lst = ["svshape 7, 0, 0, 7, 0", - 77 "svremap 31, 1, 0, 0, 0, 0, 0", # different order - 78 "sv.subf *0, *8, *16" - 79 ] + 75 # test_sv_remap2 + 76 svshape 7, 0, 0, 7, 0 + 77 svremap 31, 1, 0, 0, 0, 0, 0 # different order + 78 sv.subf *0, *8, *16 + 79 80 REMAP sv.subf RT,RA,RB - inverted application of RA/RB 81 left/right due to subf ```