From: Jacob Lifshay Date: Mon, 26 Sep 2022 21:56:17 +0000 (-0700) Subject: pcdec.: swap RA/RB to match openpower-isa.git X-Git-Tag: opf_rfc_ls005_v1~279 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e92b149c169761a1f5084e90135c685b69fe68ab;p=libreriscv.git pcdec.: swap RA/RB to match openpower-isa.git --- diff --git a/openpower/prefix_codes.mdwn b/openpower/prefix_codes.mdwn index 108fba607..24a993b52 100644 --- a/openpower/prefix_codes.mdwn +++ b/openpower/prefix_codes.mdwn @@ -25,10 +25,10 @@ Links: if `imm` is 1, at most one code-word is decoded -- useful for things like DEFLATE that alternate code words with other bits, or use multiple binary code trees. if `imm` is 0, it decodes multiple code-words -The binary code tree is encoded in `RA` like so: +The binary code tree is encoded in `RB` like so: ``` -t[i] = (RA >> i) & 0x1 +t[i] = (RB >> i) & 0x1 | +-----------+-----------+ @@ -48,7 +48,7 @@ t[8] t[9] t[10] t[11] t[12] t[13] t[14] t[15] and so on for t[16..] ``` -Decoding a code word works by walking on the tree from the root to the children, matching each passed 0 or 1 to the next read input bit in RB in LSB to MSB order. When `t[i]` is set, then a valid code word was read and `i` is written to the next byte of output in RT in LSB to MSB order. When no set `t[i]` is encountered, and there are still input bits left, then the code word is >6-bits, so SO/OV/OV32 are set, and decoding stops. +Decoding a code word works by walking on the tree from the root to the children, matching each passed 0 or 1 to the next read input bit in RA in LSB to MSB order. When `t[i]` is set, then a valid code word was read and `i` is written to the next byte of output in RT in LSB to MSB order. When no set `t[i]` is encountered, and there are still input bits left, then the code word is >6-bits, so SO/OV/OV32 are set, and decoding stops. [[!inline pages="openpower/isa/prefix_codes" quick="yes" raw="yes" ]]