From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 15 May 2020 19:04:47 +0000 (+0100)
Subject: flip over to CompBROpSubset
X-Git-Tag: div_pipeline~1179
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e9368d51081f30c044496d5edcc8e218c84c51cd;p=soc.git

flip over to CompBROpSubset
---

diff --git a/src/soc/branch/formal/proof_input_stage.py b/src/soc/branch/formal/proof_input_stage.py
index bb62fb67..fb097c87 100644
--- a/src/soc/branch/formal/proof_input_stage.py
+++ b/src/soc/branch/formal/proof_input_stage.py
@@ -8,7 +8,7 @@ from nmigen.cli import rtlil
 
 from soc.alu.input_stage import ALUInputStage
 from soc.alu.pipe_data import ALUPipeSpec
-from soc.alu.alu_input_record import CompALUOpSubset
+from soc.branch.br_input_record import CompBROpSubset
 from soc.decoder.power_enums import InternalOp
 import unittest
 
@@ -24,7 +24,7 @@ class Driver(Elaboratable):
         m = Module()
         comb = m.d.comb
 
-        rec = CompALUOpSubset()
+        rec = CompBROpSubset()
         recwidth = 0
         # Setup random inputs for dut.op
         for p in rec.ports():
@@ -41,11 +41,9 @@ class Driver(Elaboratable):
                  dut.i.b.eq(b),
                  a.eq(AnyConst(64)),
                  b.eq(AnyConst(64))]
-                      
 
         comb += dut.i.ctx.op.eq(rec)
 
-
         # Assert that op gets copied from the input to output
         for p in rec.ports():
             name = p.name
@@ -64,9 +62,6 @@ class Driver(Elaboratable):
         with m.Else():
             comb += Assert(dut.o.b == b)
 
-
-
-
         return m
 
 class GTCombinerTestCase(FHDLTestCase):
diff --git a/src/soc/branch/test/test_pipe_caller.py b/src/soc/branch/test/test_pipe_caller.py
index bbebf613..dacc50d9 100644
--- a/src/soc/branch/test/test_pipe_caller.py
+++ b/src/soc/branch/test/test_pipe_caller.py
@@ -13,7 +13,7 @@ from soc.decoder.isa.all import ISA
 
 
 from soc.branch.pipeline import BranchBasePipe
-from soc.alu.alu_input_record import CompALUOpSubset
+from soc.branch.br_input_record import CompBROpSubset
 from soc.alu.pipe_data import ALUPipeSpec
 import random
 
@@ -82,7 +82,7 @@ class BranchTestCase(FHDLTestCase):
         
 
     def test_ilang(self):
-        rec = CompALUOpSubset()
+        rec = CompBROpSubset()
 
         pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
         alu = BranchBasePipe(pspec)
@@ -105,7 +105,7 @@ class TestRunner(FHDLTestCase):
 
         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 
-        rec = CompALUOpSubset()
+        rec = CompBROpSubset()
 
         pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
         m.submodules.branch = branch = BranchBasePipe(pspec)