From: whitequark <whitequark@whitequark.org>
Date: Thu, 6 Feb 2020 16:22:22 +0000 (+0000)
Subject: write_verilog: dump $mem cell attributes.
X-Git-Tag: working-ls180~811^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e95a8ba763999b9cce480a3aadf9fae206650f00;p=yosys.git

write_verilog: dump $mem cell attributes.

The Verilog backend already dumps attributes on RTLIL::Memory objects
but not on `$mem` cells.
---

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 54d0f6148..682c47a1f 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1066,6 +1066,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		//  initial begin
 		//    memid[0] = ...
 		//  end
+		dump_attributes(f, indent.c_str(), cell->attributes);
 		f << stringf("%s" "reg [%d:%d] %s [%d:%d];\n", indent.c_str(), width-1, 0, mem_id.c_str(), size+offset-1, offset);
 		if (use_init)
 		{