From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 8 May 2020 16:55:24 +0000 (+0100)
Subject: add JTAG to minimum set
X-Git-Tag: convert-csv-opcode-to-binary~2692
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e97b89dbca257a6445dc067e5a7ce36f3ad88aea;p=libreriscv.git

add JTAG to minimum set
---

diff --git a/180nm_Oct2020.mdwn b/180nm_Oct2020.mdwn
index b1a8b3ccd..89002eec7 100644
--- a/180nm_Oct2020.mdwn
+++ b/180nm_Oct2020.mdwn
@@ -20,9 +20,9 @@ To be expanded with links to bugreports
 * a very very basic Common Data Bus infrastructure.
 * a TLB and MMU are not strictly essential (not for a proof-of-concept ASIC)
 * neither in some ways is a L1 cache
-* [[180nm_Oct2020/interfaces]] we need as a bare minimum include GPIO, EINT, SPI and QSPI,
-  I2C, UART16550, LPC (from Raptor Engineering) and that actually might
-  even be it.
+* [[180nm_Oct2020/interfaces]] we need as a bare minimum include JTAG,
+  GPIO, EINT, SPI and QSPI, I2C, UART16550, LPC (from Raptor Engineering)
+  and that actually might even be it.
 
 ## Secondary priorities
 
diff --git a/180nm_Oct2020/interfaces.mdwn b/180nm_Oct2020/interfaces.mdwn
index eda03f060..685e3bdeb 100644
--- a/180nm_Oct2020/interfaces.mdwn
+++ b/180nm_Oct2020/interfaces.mdwn
@@ -11,6 +11,7 @@ These are bare minimum viability:
 * [[shakti/m_class/QSPI]]
 * [[shakti/m_class/LPC]]
 * [[shakti/m_class/EINT]]
+* [[shakti/m_class/JTAG]]
 
 Under consideration: