From: Florent Kermarrec Date: Mon, 22 Apr 2019 06:32:00 +0000 (+0200) Subject: travis: simplify, enable and add RISC-V toolchain to build targets X-Git-Tag: 24jan2021_ls180~1310 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e98ac680c1dbb14ebbd0d19d7e5e5a1d3aa13cad;p=litex.git travis: simplify, enable and add RISC-V toolchain to build targets --- diff --git a/.travis-build-socs.sh b/.travis-build-socs.sh deleted file mode 100755 index 54cd4301..00000000 --- a/.travis-build-socs.sh +++ /dev/null @@ -1,51 +0,0 @@ -#!/usr/bin/env bash - -set -e - -# Some colors, use it like following; -# echo -e "Hello ${YELLOW}yellow${NC}" -GRAY='\033[0;30m' -GREEN='\033[0;32m' -YELLOW='\033[0;33m' -PURPLE='\033[0;35m' -NC='\033[0m' # No Color - -SPACER="echo -e ${GRAY} - ${NC}" - -travis_fold start "environment.create" -travis_time_start -echo -e "Setting up basic ${YELLOW}conda environment${NC}" -echo "-------------------------------------------------------------------" -conda env create -f environment.yml -source activate litex -echo "-------------------------------------------------------------------" -travis_time_finish -travis_fold end "environment.create" - -$SPACER - -SOC_FILES=$(find litex/boards/targets -name \*.py | grep -v sim | grep -v "__") - -COUNT=4 - -for SOC_FILE in $SOC_FILES; do - SOC=$(echo $SOC_FILE | sed -e's/\.py$//' -e's-/-.-g') - TARGET=$(echo $SOC | sed -e's/.*\.//') - - travis_fold start "$SOC.1" - travis_time_start - echo -e "Building ${GREEN}${TARGET}${NC} (${PURPLE}${SOC}${NC})" - echo "-------------------------------------------------------------------" - python -m $SOC --no-compile-gateware - echo "-------------------------------------------------------------------" - travis_time_finish - travis_fold end "$SOC.1" - travis_fold start "$SOC.2" - echo -e "Output of building ${GREEN}${TARGET}${NC} (${PURPLE}${SOC}${NC})" - echo "-------------------------------------------------------------------" - find soc_*$TARGET* | sort - echo "-------------------------------------------------------------------" - travis_fold end "$SOC.2" - - $SPACER -done diff --git a/.travis.yml b/.travis.yml index f870e95e..265ad9a9 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,19 +1,16 @@ language: python -python: - - "3.6" +dist: Xenial +python: "3.6" install: - - wget https://repo.continuum.io/miniconda/Miniconda3-latest-Linux-x86_64.sh -O miniconda.sh - - bash miniconda.sh -b -p $HOME/miniconda - - export PATH="$HOME/miniconda/bin:$PATH" - - hash -r - - conda config --set always_yes yes --set changeps1 no + # Get Migen / LiteX / Cores + - wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py + - python3 litex_setup.py init install before_script: - - export -f travis_nanoseconds - - export -f travis_fold - - export -f travis_time_start - - export -f travis_time_finish + # Get RISC-V toolchain + - wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6.tar.gz + - tar -xvf riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6.tar.gz + - export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6/bin/ -script: - - ./.travis-build-socs.sh +script: python setup.py test diff --git a/README b/README index ee4d46c7..bee291c5 100644 --- a/README +++ b/README @@ -87,23 +87,6 @@ Migen documentation can be found here: https://m-labs.hk/migen/manual FPGA lessons/tutorials can be found at: https://github.com/enjoy-digital/fpga_101 -[> Medium Quick start guide with Conda ------------------------------------------ - -0. Get miniconda by following instructions at https://conda.io/miniconda.html - -1. Clone LiteX - git clone --recurse-submodules https://github.com/enjoy-digital/litex.git - -2. Create a LiteX environment from environment.yml - conda env create -f environment.yml - -3. Enter conda environment - conda activate litex - -4. Build the target of your board...: - Go to boards/targets and execute the target you want to build - [> Quick start guide (for advanced users) ----------------------------------------- diff --git a/environment.yml b/environment.yml deleted file mode 100644 index 262e56bd..00000000 --- a/environment.yml +++ /dev/null @@ -1,13 +0,0 @@ -name: litex -channels: - - timvideos -dependencies: - - python=3.6 - - pip - - binutils-lm32-elf - - gcc-lm32-elf-nostdc - - pip: - - git+https://github.com/m-labs/migen.git#egg=migen - - -e . - - git+https://github.com/enjoy-digital/liteeth.git#egg=liteeth - - git+https://github.com/enjoy-digital/litedram.git#egg=litedram diff --git a/test/test_targets.py b/test/test_targets.py index d143bcf0..ccbba1b1 100644 --- a/test/test_targets.py +++ b/test/test_targets.py @@ -18,53 +18,54 @@ def build_test(socs): class TestTargets(unittest.TestCase): + kwargs = {"cpu_type": "vexriscv"} # altera boards def test_de0nano(self): from litex.boards.targets.de0nano import BaseSoC - errors = build_test([BaseSoC()]) + errors = build_test([BaseSoC(**self.kwargs)]) self.assertEqual(errors, 0) # xilinx boards def test_minispartan6(self): from litex.boards.targets.minispartan6 import BaseSoC - errors = build_test([BaseSoC()]) + errors = build_test([BaseSoC(**self.kwargs)]) self.assertEqual(errors, 0) def test_arty(self): from litex.boards.targets.arty import BaseSoC, EthernetSoC - errors = build_test([BaseSoC(), EthernetSoC()]) + errors = build_test([BaseSoC(**self.kwargs), EthernetSoC(**self.kwargs)]) self.assertEqual(errors, 0) def test_nexys4ddr(self): from litex.boards.targets.nexys4ddr import BaseSoC - errors = build_test([BaseSoC()]) + errors = build_test([BaseSoC(**self.kwargs)]) self.assertEqual(errors, 0) def test_nexys_video(self): from litex.boards.targets.nexys_video import BaseSoC, EthernetSoC - errors = build_test([BaseSoC(), EthernetSoC()]) + errors = build_test([BaseSoC(**self.kwargs), EthernetSoC(**self.kwargs)]) self.assertEqual(errors, 0) def test_genesys2(self): from litex.boards.targets.genesys2 import BaseSoC, EthernetSoC - errors = build_test([BaseSoC(), EthernetSoC()]) + errors = build_test([BaseSoC(**self.kwargs), EthernetSoC(**self.kwargs)]) self.assertEqual(errors, 0) def test_kc705(self): from litex.boards.targets.kc705 import BaseSoC, EthernetSoC - errors = build_test([BaseSoC(), EthernetSoC()]) + errors = build_test([BaseSoC(**self.kwargs), EthernetSoC(**self.kwargs)]) self.assertEqual(errors, 0) # lattice boards def test_versa_ecp5(self): from litex.boards.targets.versa_ecp5 import BaseSoC - errors = build_test([BaseSoC()]) + errors = build_test([BaseSoC(**self.kwargs)]) self.assertEqual(errors, 0) def test_versa_ulx3s(self): from litex.boards.targets.ulx3s import BaseSoC - errors = build_test([BaseSoC()]) + errors = build_test([BaseSoC(**self.kwargs)]) self.assertEqual(errors, 0) # build simple design for all platforms @@ -85,6 +86,7 @@ class TestTargets(unittest.TestCase): ] for p in platforms: os.system("litex_simple litex.boards.platforms." + p + + " --cpu-type=vexriscv " + " --no-compile-software " + " --no-compile-gateware " + " --uart-stub=True")