From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 16 Dec 2019 21:01:51 +0000 (-0800)
Subject: Merge blockram tests
X-Git-Tag: working-ls180~922^2~7
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e990c013c57da8149dbbd2fe2633e953ec8f471b;p=yosys.git

Merge blockram tests
---

diff --git a/tests/arch/common/blockram.v b/tests/arch/common/blockram.v
new file mode 100644
index 000000000..dbc6ca65c
--- /dev/null
+++ b/tests/arch/common/blockram.v
@@ -0,0 +1,45 @@
+`default_nettype none
+module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
+   (input  wire                      write_enable, clk,
+    input  wire  [DATA_WIDTH-1:0]    data_in,
+    input  wire  [ADDRESS_WIDTH-1:0] address_in,
+    output wire  [DATA_WIDTH-1:0]    data_out);
+
+   localparam WORD  = (DATA_WIDTH-1);
+   localparam DEPTH = (2**ADDRESS_WIDTH-1);
+
+   reg [WORD:0] data_out_r;
+   reg [WORD:0] memory [0:DEPTH];
+
+   always @(posedge clk) begin
+      if (write_enable)
+        memory[address_in] <= data_in;
+      data_out_r <= memory[address_in];
+   end
+
+   assign data_out = data_out_r;
+endmodule // sync_ram_sp
+
+
+`default_nettype none
+module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
+   (input  wire                      clk, write_enable,
+    input  wire  [DATA_WIDTH-1:0]    data_in,
+    input  wire  [ADDRESS_WIDTH-1:0] address_in_r, address_in_w,
+    output wire  [DATA_WIDTH-1:0]    data_out);
+
+   localparam WORD  = (DATA_WIDTH-1);
+   localparam DEPTH = (2**ADDRESS_WIDTH-1);
+
+   reg [WORD:0] data_out_r;
+   reg [WORD:0] memory [0:DEPTH];
+
+   always @(posedge clk) begin
+      if (write_enable)
+        memory[address_in_w] <= data_in;
+      data_out_r <= memory[address_in_r];
+   end
+
+   assign data_out = data_out_r;
+endmodule // sync_ram_sdp
+
diff --git a/tests/arch/common/blockram_params.v b/tests/arch/common/blockram_params.v
deleted file mode 100644
index dbc6ca65c..000000000
--- a/tests/arch/common/blockram_params.v
+++ /dev/null
@@ -1,45 +0,0 @@
-`default_nettype none
-module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
-   (input  wire                      write_enable, clk,
-    input  wire  [DATA_WIDTH-1:0]    data_in,
-    input  wire  [ADDRESS_WIDTH-1:0] address_in,
-    output wire  [DATA_WIDTH-1:0]    data_out);
-
-   localparam WORD  = (DATA_WIDTH-1);
-   localparam DEPTH = (2**ADDRESS_WIDTH-1);
-
-   reg [WORD:0] data_out_r;
-   reg [WORD:0] memory [0:DEPTH];
-
-   always @(posedge clk) begin
-      if (write_enable)
-        memory[address_in] <= data_in;
-      data_out_r <= memory[address_in];
-   end
-
-   assign data_out = data_out_r;
-endmodule // sync_ram_sp
-
-
-`default_nettype none
-module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
-   (input  wire                      clk, write_enable,
-    input  wire  [DATA_WIDTH-1:0]    data_in,
-    input  wire  [ADDRESS_WIDTH-1:0] address_in_r, address_in_w,
-    output wire  [DATA_WIDTH-1:0]    data_out);
-
-   localparam WORD  = (DATA_WIDTH-1);
-   localparam DEPTH = (2**ADDRESS_WIDTH-1);
-
-   reg [WORD:0] data_out_r;
-   reg [WORD:0] memory [0:DEPTH];
-
-   always @(posedge clk) begin
-      if (write_enable)
-        memory[address_in_w] <= data_in;
-      data_out_r <= memory[address_in_r];
-   end
-
-   assign data_out = data_out_r;
-endmodule // sync_ram_sdp
-
diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys
new file mode 100644
index 000000000..362d33229
--- /dev/null
+++ b/tests/arch/xilinx/blockram.ys
@@ -0,0 +1,81 @@
+### TODO: Not running equivalence checking because BRAM models does not exists
+###       currently. Checking instance counts instead.
+## Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1
+#read_verilog ../common/blockram.v
+#chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp
+#synth_xilinx -top sync_ram_sdp
+#cd sync_ram_sdp
+#select -assert-count 1 t:RAMB18E1
+#
+#design -reset
+#read_verilog ../common/blockram.v
+#chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp
+#synth_xilinx -top sync_ram_sdp
+#cd sync_ram_sdp
+#select -assert-count 1 t:RAMB18E1
+#
+#design -reset
+#read_verilog ../common/blockram.v
+#chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp
+#synth_xilinx -top sync_ram_sdp
+#cd sync_ram_sdp
+#select -assert-count 1 t:RAMB18E1
+#
+#design -reset
+#read_verilog ../common/blockram.v
+#chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
+#synth_xilinx -top sync_ram_sdp
+#cd sync_ram_sdp
+#select -assert-count 1 t:RAMB18E1
+#
+## Anything memory bits < 1024 -> LUTRAM
+#design -reset
+#read_verilog ../common/blockram.v
+#chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp
+#synth_xilinx -top sync_ram_sdp
+#cd sync_ram_sdp
+#select -assert-count 0 t:RAMB18E1
+#select -assert-count 4 t:RAM128X1D
+#
+## More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 
+#design -reset
+#read_verilog ../common/blockram.v
+#chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp
+#synth_xilinx -top sync_ram_sdp
+#cd sync_ram_sdp
+#select -assert-count 1 t:RAMB36E1
+#
+#
+#### With parameters
+
+design -reset
+read_verilog ../common/blockram.v
+hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 
+setattr -set ram_style "block" m:memory
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 1 t:RAMB18E1
+
+design -reset
+read_verilog ../common/blockram.v
+hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 
+setattr -set ram_block 1 m:memory
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 1 t:RAMB18E1
+
+design -reset
+read_verilog ../common/blockram.v
+hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 
+setattr -set ram_style "dont_infer_a_ram_pretty_please" m:memory
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 0 t:RAMB18E1
+
+design -reset
+read_verilog ../common/blockram.v
+hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 
+setattr -set logic_block 1 m:memory
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 0 t:RAMB18E1
diff --git a/tests/arch/xilinx/blockram_params.ys b/tests/arch/xilinx/blockram_params.ys
deleted file mode 100644
index 27a94834e..000000000
--- a/tests/arch/xilinx/blockram_params.ys
+++ /dev/null
@@ -1,47 +0,0 @@
-## TODO: Not running equivalence checking because BRAM models does not exists
-##       currently. Checking instance counts instead.
-# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1
-read_verilog ../common/blockram_params.v
-chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp
-synth_xilinx -top sync_ram_sdp
-cd sync_ram_sdp
-select -assert-count 1 t:RAMB18E1
-
-design -reset
-read_verilog ../common/blockram_params.v
-chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp
-synth_xilinx -top sync_ram_sdp
-cd sync_ram_sdp
-select -assert-count 1 t:RAMB18E1
-
-design -reset
-read_verilog ../common/blockram_params.v
-chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp
-synth_xilinx -top sync_ram_sdp
-cd sync_ram_sdp
-select -assert-count 1 t:RAMB18E1
-
-design -reset
-read_verilog ../common/blockram_params.v
-chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
-synth_xilinx -top sync_ram_sdp
-cd sync_ram_sdp
-select -assert-count 1 t:RAMB18E1
-
-# Anything memory bits < 1024 -> LUTRAM
-design -reset
-read_verilog ../common/blockram_params.v
-chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp
-synth_xilinx -top sync_ram_sdp
-cd sync_ram_sdp
-select -assert-count 0 t:RAMB18E1
-select -assert-count 4 t:RAM128X1D
-
-# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 
-design -reset
-read_verilog ../common/blockram_params.v
-chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp
-synth_xilinx -top sync_ram_sdp
-cd sync_ram_sdp
-select -assert-count 1 t:RAMB36E1
-