From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 13 Jul 2019 02:33:02 +0000 (-0700)
Subject: duplicate -> clone
X-Git-Tag: working-ls180~1190^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e9bdc86c0e0ea41d1ee8a610b7f1304c3eaf43e9;p=yosys.git

duplicate -> clone
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 36f2fafc3..4a6ec3a47 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -761,11 +761,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 
 			auto jt = bit2sinks.find(a_bit);
 			if (jt == bit2sinks.end())
-				goto duplicate_lut;
+				goto clone_lut;
 
 			for (auto sink_cell : jt->second)
 				if (sink_cell->type != "$lut")
-					goto duplicate_lut;
+					goto clone_lut;
 
 			// Push downstream LUTs past inverter
 			for (auto sink_cell : jt->second) {
@@ -787,7 +787,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 				sink_cell->setParam("\\LUT", mask);
 			}
 
-duplicate_lut:
+clone_lut:
 			driver_mask = driver_lut->getParam("\\LUT");
 			for (auto &b : driver_mask.bits) {
 				if (b == RTLIL::State::S0) b = RTLIL::State::S1;