From: colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0 <colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0@web>
Date: Mon, 16 Nov 2020 18:13:37 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1763
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e9c187b6ceb03e371ec7e9f4a90c004b0dc549b3;p=libreriscv.git

---

diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index dd336a50f..541dc928b 100644
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -14,10 +14,11 @@ TODO checklist based on above
 
 | Done?   | FPGA IO PAD |
 |---------|-------------|
-|         |    Hello    |
-|         |    Motto    |
-|         |    Frodo    |
-|         |    Dodo
+|         | For god's sake do not get this wrong |
+|         | ***DO NOT*** drive an input as an output or vice-versa |
+|         | ***DO NOT*** wire up 5.0V to GND with the jumper-cables |
+|         | ***DO NOT*** randomly upload and power up the FPGA until this has been ***THOROUGHLY*** triple-checked |
+|         | If you violate any of the above stated hard-and-fast rules you will end up learning the hard way by **DESTROYING** the FPGA.
 
 ## Connecting the dots: