From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 12 Jun 2008 04:53:50 +0000 (-0400)
Subject: X86: Make the logical destination and destination format work.
X-Git-Tag: m5_2.0_beta6~145
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e9c481ea4ae7d72d6a53bc80c7f867578179f00c;p=gem5.git

X86: Make the logical destination and destination format work.
---

diff --git a/src/arch/x86/miscregfile.cc b/src/arch/x86/miscregfile.cc
index d52d56915..46ee3a7db 100644
--- a/src/arch/x86/miscregfile.cc
+++ b/src/arch/x86/miscregfile.cc
@@ -106,6 +106,8 @@ void MiscRegFile::clear()
 {
     // Blank everything. 0 might not be an appropriate value for some things.
     memset(regVal, 0, NumMiscRegs * sizeof(MiscReg));
+    //Set the local apic DFR to the flat model.
+    regVal[MISCREG_APIC_DESTINATION_FORMAT] = (MiscReg)(-1);
 }
 
 MiscReg MiscRegFile::readRegNoEffect(int miscReg)
@@ -151,12 +153,6 @@ MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
           case MISCREG_APIC_EOI:
             panic("Local APIC EOI register unimplemented.\n");
             break;
-          case MISCREG_APIC_LOGICAL_DESTINATION:
-            panic("Local APIC Logical Destination register unimplemented.\n");
-            break;
-          case MISCREG_APIC_DESTINATION_FORMAT:
-            panic("Local APIC Destination Format register unimplemented.\n");
-            break;
           case MISCREG_APIC_ERROR_STATUS:
             regVal[MISCREG_APIC_INTERNAL_STATE] &= ~ULL(0x1);
             break;
@@ -237,10 +233,10 @@ void MiscRegFile::setReg(int miscReg,
             panic("Local APIC EOI register unimplemented.\n");
             break;
           case MISCREG_APIC_LOGICAL_DESTINATION:
-            panic("Local APIC Logical Destination register unimplemented.\n");
+            newVal = val & 0xFF000000;
             break;
           case MISCREG_APIC_DESTINATION_FORMAT:
-            panic("Local APIC Destination Format register unimplemented.\n");
+            newVal = val | 0x0FFFFFFF;
             break;
           case MISCREG_APIC_SPURIOUS_INTERRUPT_VECTOR:
             regVal[MISCREG_APIC_INTERNAL_STATE] &= ~ULL(1 << 1);