From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 17 Jan 2022 17:59:59 +0000 (+0000)
Subject: connect up DEC/TB FSM pauser from core to Issuer
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e9cf4def637bcd541c1c06444eda332c079608b8;p=soc.git

connect up DEC/TB FSM pauser from core to Issuer
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index e11f3d35..ab21b1b9 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -396,6 +396,10 @@ class TestIssuerBase(Elaboratable):
                 m.submodules["sram4k_%d" % i] = csd(sram)
                 comb += sram.enable.eq(self.wb_sram_en)
 
+        # terrible hack to stop a potential race condition.  if core
+        # is doing any operation (at all) pause the DEC/TB FSM
+        comb += self.pause_dec_tb.eq(core.pause_dec_tb)
+
         # XICS interrupt handler
         if self.xics:
             m.submodules.xics_icp = icp = csd(self.xics_icp)