From: Richard Sandiford Date: Tue, 30 Nov 2021 17:50:25 +0000 (+0000) Subject: aarch64: Add missing system registers [PR27145] X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e9dac4f0125752f64f7fa76ff4208a3b56493a19;p=binutils-gdb.git aarch64: Add missing system registers [PR27145] This patch adds support for various system registers, up to Armv8.7-A. This includes all the registers that were mentioned in the PR and that hadn't become supported since. opcodes/ PR aarch64/27145 * aarch64-opc.c (SR_V8_4): Remove duplicate definition. (SR_V8_6, SR_V8_7, SR_GIC, SR_AMU): New macros. (aarch64_sys_regs): Add missing entries (up to Armv8.7-A). gas/ PR aarch64/27145 * testsuite/gas/aarch64/sysreg-8.s, * testsuite/gas/aarch64/sysreg-8.d, * testsuite/gas/aarch64/illegal-sysreg-8.s, * testsuite/gas/aarch64/illegal-sysreg-8.d, * testsuite/gas/aarch64/illegal-sysreg-8.l, * testsuite/gas/aarch64/illegal-sysreg-8b.s, * testsuite/gas/aarch64/illegal-sysreg-8b.d, * testsuite/gas/aarch64/illegal-sysreg-8b.l: New tests. * testsuite/gas/aarch64/sysreg.s: Change system register numbers to ones that are still unallocated. * testsuite/gas/aarch64/sysreg.d: Update accordingly. --- diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-8.d b/gas/testsuite/gas/aarch64/illegal-sysreg-8.d new file mode 100644 index 00000000000..f0c0d6030ad --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-sysreg-8.d @@ -0,0 +1 @@ +#error_output: illegal-sysreg-8.l diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-8.l b/gas/testsuite/gas/aarch64/illegal-sysreg-8.l new file mode 100644 index 00000000000..8215a07900f --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-sysreg-8.l @@ -0,0 +1,185 @@ +.*: Assembler messages: +.*: Error: selected processor does not support system register name 'lorid_el1' +.*: Error: selected processor does not support system register name 'ccsidr2_el1' +.*: Error: selected processor does not support system register name 'trfcr_el1' +.*: Error: selected processor does not support system register name 'trfcr_el1' +.*: Error: selected processor does not support system register name 'pmmir_el1' +.*: Error: selected processor does not support system register name 'trfcr_el2' +.*: Error: selected processor does not support system register name 'trfcr_el2' +.*: Error: selected processor does not support system register name 'trfcr_el12' +.*: Error: selected processor does not support system register name 'trfcr_el12' +.*: Error: selected processor does not support system register name 'amcr_el0' +.*: Error: selected processor does not support system register name 'amcr_el0' +.*: Error: selected processor does not support system register name 'amcfgr_el0' +.*: Error: selected processor does not support system register name 'amcgcr_el0' +.*: Error: selected processor does not support system register name 'amuserenr_el0' +.*: Error: selected processor does not support system register name 'amuserenr_el0' +.*: Error: selected processor does not support system register name 'amcntenclr0_el0' +.*: Error: selected processor does not support system register name 'amcntenclr0_el0' +.*: Error: selected processor does not support system register name 'amcntenset0_el0' +.*: Error: selected processor does not support system register name 'amcntenset0_el0' +.*: Error: selected processor does not support system register name 'amcntenclr1_el0' +.*: Error: selected processor does not support system register name 'amcntenclr1_el0' +.*: Error: selected processor does not support system register name 'amcntenset1_el0' +.*: Error: selected processor does not support system register name 'amcntenset1_el0' +.*: Error: selected processor does not support system register name 'amevcntr00_el0' +.*: Error: selected processor does not support system register name 'amevcntr00_el0' +.*: Error: selected processor does not support system register name 'amevcntr01_el0' +.*: Error: selected processor does not support system register name 'amevcntr01_el0' +.*: Error: selected processor does not support system register name 'amevcntr02_el0' +.*: Error: selected processor does not support system register name 'amevcntr02_el0' +.*: Error: selected processor does not support system register name 'amevcntr03_el0' +.*: Error: selected processor does not support system register name 'amevcntr03_el0' +.*: Error: selected processor does not support system register name 'amevtyper00_el0' +.*: Error: selected processor does not support system register name 'amevtyper01_el0' +.*: Error: selected processor does not support system register name 'amevtyper02_el0' +.*: Error: selected processor does not support system register name 'amevtyper03_el0' +.*: Error: selected processor does not support system register name 'amevcntr10_el0' +.*: Error: selected processor does not support system register name 'amevcntr10_el0' +.*: Error: selected processor does not support system register name 'amevcntr11_el0' +.*: Error: selected processor does not support system register name 'amevcntr11_el0' +.*: Error: selected processor does not support system register name 'amevcntr12_el0' +.*: Error: selected processor does not support system register name 'amevcntr12_el0' +.*: Error: selected processor does not support system register name 'amevcntr13_el0' +.*: Error: selected processor does not support system register name 'amevcntr13_el0' +.*: Error: selected processor does not support system register name 'amevcntr14_el0' +.*: Error: selected processor does not support system register name 'amevcntr14_el0' +.*: Error: selected processor does not support system register name 'amevcntr15_el0' +.*: Error: selected processor does not support system register name 'amevcntr15_el0' +.*: Error: selected processor does not support system register name 'amevcntr16_el0' +.*: Error: selected processor does not support system register name 'amevcntr16_el0' +.*: Error: selected processor does not support system register name 'amevcntr17_el0' +.*: Error: selected processor does not support system register name 'amevcntr17_el0' +.*: Error: selected processor does not support system register name 'amevcntr18_el0' +.*: Error: selected processor does not support system register name 'amevcntr18_el0' +.*: Error: selected processor does not support system register name 'amevcntr19_el0' +.*: Error: selected processor does not support system register name 'amevcntr19_el0' +.*: Error: selected processor does not support system register name 'amevcntr110_el0' +.*: Error: selected processor does not support system register name 'amevcntr110_el0' +.*: Error: selected processor does not support system register name 'amevcntr111_el0' +.*: Error: selected processor does not support system register name 'amevcntr111_el0' +.*: Error: selected processor does not support system register name 'amevcntr112_el0' +.*: Error: selected processor does not support system register name 'amevcntr112_el0' +.*: Error: selected processor does not support system register name 'amevcntr113_el0' +.*: Error: selected processor does not support system register name 'amevcntr113_el0' +.*: Error: selected processor does not support system register name 'amevcntr114_el0' +.*: Error: selected processor does not support system register name 'amevcntr114_el0' +.*: Error: selected processor does not support system register name 'amevcntr115_el0' +.*: Error: selected processor does not support system register name 'amevcntr115_el0' +.*: Error: selected processor does not support system register name 'amevtyper10_el0' +.*: Error: selected processor does not support system register name 'amevtyper10_el0' +.*: Error: selected processor does not support system register name 'amevtyper11_el0' +.*: Error: selected processor does not support system register name 'amevtyper11_el0' +.*: Error: selected processor does not support system register name 'amevtyper12_el0' +.*: Error: selected processor does not support system register name 'amevtyper12_el0' +.*: Error: selected processor does not support system register name 'amevtyper13_el0' +.*: Error: selected processor does not support system register name 'amevtyper13_el0' +.*: Error: selected processor does not support system register name 'amevtyper14_el0' +.*: Error: selected processor does not support system register name 'amevtyper14_el0' +.*: Error: selected processor does not support system register name 'amevtyper15_el0' +.*: Error: selected processor does not support system register name 'amevtyper15_el0' +.*: Error: selected processor does not support system register name 'amevtyper16_el0' +.*: Error: selected processor does not support system register name 'amevtyper16_el0' +.*: Error: selected processor does not support system register name 'amevtyper17_el0' +.*: Error: selected processor does not support system register name 'amevtyper17_el0' +.*: Error: selected processor does not support system register name 'amevtyper18_el0' +.*: Error: selected processor does not support system register name 'amevtyper18_el0' +.*: Error: selected processor does not support system register name 'amevtyper19_el0' +.*: Error: selected processor does not support system register name 'amevtyper19_el0' +.*: Error: selected processor does not support system register name 'amevtyper110_el0' +.*: Error: selected processor does not support system register name 'amevtyper110_el0' +.*: Error: selected processor does not support system register name 'amevtyper111_el0' +.*: Error: selected processor does not support system register name 'amevtyper111_el0' +.*: Error: selected processor does not support system register name 'amevtyper112_el0' +.*: Error: selected processor does not support system register name 'amevtyper112_el0' +.*: Error: selected processor does not support system register name 'amevtyper113_el0' +.*: Error: selected processor does not support system register name 'amevtyper113_el0' +.*: Error: selected processor does not support system register name 'amevtyper114_el0' +.*: Error: selected processor does not support system register name 'amevtyper114_el0' +.*: Error: selected processor does not support system register name 'amevtyper115_el0' +.*: Error: selected processor does not support system register name 'amevtyper115_el0' +.*: Error: selected processor does not support system register name 'amcg1idr_el0' +.*: Error: selected processor does not support system register name 'cntpctss_el0' +.*: Error: selected processor does not support system register name 'cntvctss_el0' +.*: Error: selected processor does not support system register name 'hfgrtr_el2' +.*: Error: selected processor does not support system register name 'hfgrtr_el2' +.*: Error: selected processor does not support system register name 'hfgwtr_el2' +.*: Error: selected processor does not support system register name 'hfgwtr_el2' +.*: Error: selected processor does not support system register name 'hfgitr_el2' +.*: Error: selected processor does not support system register name 'hfgitr_el2' +.*: Error: selected processor does not support system register name 'hdfgrtr_el2' +.*: Error: selected processor does not support system register name 'hdfgrtr_el2' +.*: Error: selected processor does not support system register name 'hdfgwtr_el2' +.*: Error: selected processor does not support system register name 'hdfgwtr_el2' +.*: Error: selected processor does not support system register name 'hafgrtr_el2' +.*: Error: selected processor does not support system register name 'hafgrtr_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff00_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff00_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff01_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff01_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff02_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff02_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff03_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff03_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff04_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff04_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff05_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff05_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff06_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff06_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff07_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff07_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff08_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff08_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff09_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff09_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff010_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff010_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff011_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff011_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff012_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff012_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff013_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff013_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff014_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff014_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff015_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff015_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff10_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff10_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff11_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff11_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff12_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff12_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff13_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff13_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff14_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff14_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff15_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff15_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff16_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff16_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff17_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff17_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff18_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff18_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff19_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff19_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff110_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff110_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff111_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff111_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff112_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff112_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff113_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff113_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff114_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff114_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff115_el2' +.*: Error: selected processor does not support system register name 'amevcntvoff115_el2' +.*: Error: selected processor does not support system register name 'cntpoff_el2' +.*: Error: selected processor does not support system register name 'cntpoff_el2' +.*: Error: selected processor does not support system register name 'pmsnevfr_el1' +.*: Error: selected processor does not support system register name 'pmsnevfr_el1' +.*: Error: selected processor does not support system register name 'hcrx_el2' +.*: Error: selected processor does not support system register name 'hcrx_el2' diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-8.s b/gas/testsuite/gas/aarch64/illegal-sysreg-8.s new file mode 100644 index 00000000000..a1a7ae6faed --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-sysreg-8.s @@ -0,0 +1,125 @@ + .macro roreg, name + mrs x0, \name + .endm + + .macro woreg, name + msr \name, x1 + .endm + + .macro rwreg, name + mrs x2, \name + msr \name, x3 + .endm + + roreg lorid_el1 + + .arch armv8.2-a + + roreg ccsidr2_el1 + + .arch armv8.3-a + + rwreg trfcr_el1 + roreg pmmir_el1 + rwreg trfcr_el2 + + rwreg trfcr_el12 + + rwreg amcr_el0 + roreg amcfgr_el0 + roreg amcgcr_el0 + rwreg amuserenr_el0 + rwreg amcntenclr0_el0 + rwreg amcntenset0_el0 + rwreg amcntenclr1_el0 + rwreg amcntenset1_el0 + rwreg amevcntr00_el0 + rwreg amevcntr01_el0 + rwreg amevcntr02_el0 + rwreg amevcntr03_el0 + roreg amevtyper00_el0 + roreg amevtyper01_el0 + roreg amevtyper02_el0 + roreg amevtyper03_el0 + rwreg amevcntr10_el0 + rwreg amevcntr11_el0 + rwreg amevcntr12_el0 + rwreg amevcntr13_el0 + rwreg amevcntr14_el0 + rwreg amevcntr15_el0 + rwreg amevcntr16_el0 + rwreg amevcntr17_el0 + rwreg amevcntr18_el0 + rwreg amevcntr19_el0 + rwreg amevcntr110_el0 + rwreg amevcntr111_el0 + rwreg amevcntr112_el0 + rwreg amevcntr113_el0 + rwreg amevcntr114_el0 + rwreg amevcntr115_el0 + rwreg amevtyper10_el0 + rwreg amevtyper11_el0 + rwreg amevtyper12_el0 + rwreg amevtyper13_el0 + rwreg amevtyper14_el0 + rwreg amevtyper15_el0 + rwreg amevtyper16_el0 + rwreg amevtyper17_el0 + rwreg amevtyper18_el0 + rwreg amevtyper19_el0 + rwreg amevtyper110_el0 + rwreg amevtyper111_el0 + rwreg amevtyper112_el0 + rwreg amevtyper113_el0 + rwreg amevtyper114_el0 + rwreg amevtyper115_el0 + + .arch armv8.5-a + + roreg amcg1idr_el0 + roreg cntpctss_el0 + roreg cntvctss_el0 + rwreg hfgrtr_el2 + rwreg hfgwtr_el2 + rwreg hfgitr_el2 + rwreg hdfgrtr_el2 + rwreg hdfgwtr_el2 + rwreg hafgrtr_el2 + rwreg amevcntvoff00_el2 + rwreg amevcntvoff01_el2 + rwreg amevcntvoff02_el2 + rwreg amevcntvoff03_el2 + rwreg amevcntvoff04_el2 + rwreg amevcntvoff05_el2 + rwreg amevcntvoff06_el2 + rwreg amevcntvoff07_el2 + rwreg amevcntvoff08_el2 + rwreg amevcntvoff09_el2 + rwreg amevcntvoff010_el2 + rwreg amevcntvoff011_el2 + rwreg amevcntvoff012_el2 + rwreg amevcntvoff013_el2 + rwreg amevcntvoff014_el2 + rwreg amevcntvoff015_el2 + rwreg amevcntvoff10_el2 + rwreg amevcntvoff11_el2 + rwreg amevcntvoff12_el2 + rwreg amevcntvoff13_el2 + rwreg amevcntvoff14_el2 + rwreg amevcntvoff15_el2 + rwreg amevcntvoff16_el2 + rwreg amevcntvoff17_el2 + rwreg amevcntvoff18_el2 + rwreg amevcntvoff19_el2 + rwreg amevcntvoff110_el2 + rwreg amevcntvoff111_el2 + rwreg amevcntvoff112_el2 + rwreg amevcntvoff113_el2 + rwreg amevcntvoff114_el2 + rwreg amevcntvoff115_el2 + rwreg cntpoff_el2 + + .arch armv8.6-a + + rwreg pmsnevfr_el1 + rwreg hcrx_el2 diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-8b.d b/gas/testsuite/gas/aarch64/illegal-sysreg-8b.d new file mode 100644 index 00000000000..49622831e74 --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-sysreg-8b.d @@ -0,0 +1 @@ +#warning_output: illegal-sysreg-8b.l diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-8b.l b/gas/testsuite/gas/aarch64/illegal-sysreg-8b.l new file mode 100644 index 00000000000..45bd9ab15a3 --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-sysreg-8b.l @@ -0,0 +1,30 @@ +.*: Assembler messages: +.*: Warning: specified register cannot be written to at operand 1 -- `msr id_dfr1_el1,x1' +.*: Warning: specified register cannot be written to at operand 1 -- `msr id_mmfr5_el1,x1' +.*: Warning: specified register cannot be written to at operand 1 -- `msr id_isar6_el1,x1' +.*: Warning: specified register cannot be written to at operand 1 -- `msr icc_iar0_el1,x1' +.*: Warning: specified register cannot be read from at operand 2 -- `mrs x0,icc_eoir0_el1' +.*: Warning: specified register cannot be written to at operand 1 -- `msr icc_hppir0_el1,x1' +.*: Warning: specified register cannot be read from at operand 2 -- `mrs x0,icc_dir_el1' +.*: Warning: specified register cannot be written to at operand 1 -- `msr icc_rpr_el1,x1' +.*: Warning: specified register cannot be read from at operand 2 -- `mrs x0,icc_sgi1r_el1' +.*: Warning: specified register cannot be read from at operand 2 -- `mrs x0,icc_asgi1r_el1' +.*: Warning: specified register cannot be read from at operand 2 -- `mrs x0,icc_sgi0r_el1' +.*: Warning: specified register cannot be written to at operand 1 -- `msr icc_iar1_el1,x1' +.*: Warning: specified register cannot be read from at operand 2 -- `mrs x0,icc_eoir1_el1' +.*: Warning: specified register cannot be written to at operand 1 -- `msr icc_hppir1_el1,x1' +.*: Warning: specified register cannot be written to at operand 1 -- `msr ich_misr_el2,x1' +.*: Warning: specified register cannot be written to at operand 1 -- `msr ich_eisr_el2,x1' +.*: Warning: specified register cannot be written to at operand 1 -- `msr ich_elrsr_el2,x1' +.*: Warning: specified register cannot be written to at operand 1 -- `msr lorid_el1,x1' +.*: Warning: specified register cannot be written to at operand 1 -- `msr ccsidr2_el1,x1' +.*: Warning: specified register cannot be written to at operand 1 -- `msr pmmir_el1,x1' +.*: Warning: specified register cannot be written to at operand 1 -- `msr amcfgr_el0,x1' +.*: Warning: specified register cannot be written to at operand 1 -- `msr amcgcr_el0,x1' +.*: Warning: specified register cannot be written to at operand 1 -- `msr amevtyper00_el0,x1' +.*: Warning: specified register cannot be written to at operand 1 -- `msr amevtyper01_el0,x1' +.*: Warning: specified register cannot be written to at operand 1 -- `msr amevtyper02_el0,x1' +.*: Warning: specified register cannot be written to at operand 1 -- `msr amevtyper03_el0,x1' +.*: Warning: specified register cannot be written to at operand 1 -- `msr amcg1idr_el0,x1' +.*: Warning: specified register cannot be written to at operand 1 -- `msr cntpctss_el0,x1' +.*: Warning: specified register cannot be written to at operand 1 -- `msr cntvctss_el0,x1' diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-8b.s b/gas/testsuite/gas/aarch64/illegal-sysreg-8b.s new file mode 100644 index 00000000000..727c94f24dc --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-sysreg-8b.s @@ -0,0 +1,51 @@ + .macro roreg, name + msr \name, x1 + .endm + + .macro woreg, name + mrs x0, \name + .endm + + roreg id_dfr1_el1 + roreg id_mmfr5_el1 + roreg id_isar6_el1 + + roreg icc_iar0_el1 + woreg icc_eoir0_el1 + roreg icc_hppir0_el1 + woreg icc_dir_el1 + roreg icc_rpr_el1 + woreg icc_sgi1r_el1 + woreg icc_asgi1r_el1 + woreg icc_sgi0r_el1 + roreg icc_iar1_el1 + woreg icc_eoir1_el1 + roreg icc_hppir1_el1 + roreg ich_misr_el2 + roreg ich_eisr_el2 + roreg ich_elrsr_el2 + + .arch armv8.1-a + + roreg lorid_el1 + + .arch armv8.3-a + + roreg ccsidr2_el1 + + .arch armv8.4-a + + roreg pmmir_el1 + + roreg amcfgr_el0 + roreg amcgcr_el0 + roreg amevtyper00_el0 + roreg amevtyper01_el0 + roreg amevtyper02_el0 + roreg amevtyper03_el0 + + .arch armv8.6-a + + roreg amcg1idr_el0 + roreg cntpctss_el0 + roreg cntvctss_el0 diff --git a/gas/testsuite/gas/aarch64/sysreg-8.d b/gas/testsuite/gas/aarch64/sysreg-8.d new file mode 100644 index 00000000000..3be4120aae0 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sysreg-8.d @@ -0,0 +1,291 @@ +#objdump: -dr + +.* + + +Disassembly of section \.text: + +0+ <\.text>: +[^:]*: d53803a0 mrs x0, id_dfr1_el1 +[^:]*: d53803c0 mrs x0, id_mmfr5_el1 +[^:]*: d53802e0 mrs x0, id_isar6_el1 +[^:]*: d5384602 mrs x2, icc_pmr_el1 +[^:]*: d5184603 msr icc_pmr_el1, x3 +[^:]*: d538c800 mrs x0, icc_iar0_el1 +[^:]*: d518c821 msr icc_eoir0_el1, x1 +[^:]*: d538c840 mrs x0, icc_hppir0_el1 +[^:]*: d538c862 mrs x2, icc_bpr0_el1 +[^:]*: d518c863 msr icc_bpr0_el1, x3 +[^:]*: d538c882 mrs x2, icc_ap0r0_el1 +[^:]*: d518c883 msr icc_ap0r0_el1, x3 +[^:]*: d538c8a2 mrs x2, icc_ap0r1_el1 +[^:]*: d518c8a3 msr icc_ap0r1_el1, x3 +[^:]*: d538c8c2 mrs x2, icc_ap0r2_el1 +[^:]*: d518c8c3 msr icc_ap0r2_el1, x3 +[^:]*: d538c8e2 mrs x2, icc_ap0r3_el1 +[^:]*: d518c8e3 msr icc_ap0r3_el1, x3 +[^:]*: d538c902 mrs x2, icc_ap1r0_el1 +[^:]*: d518c903 msr icc_ap1r0_el1, x3 +[^:]*: d538c922 mrs x2, icc_ap1r1_el1 +[^:]*: d518c923 msr icc_ap1r1_el1, x3 +[^:]*: d538c942 mrs x2, icc_ap1r2_el1 +[^:]*: d518c943 msr icc_ap1r2_el1, x3 +[^:]*: d538c962 mrs x2, icc_ap1r3_el1 +[^:]*: d518c963 msr icc_ap1r3_el1, x3 +[^:]*: d518cb21 msr icc_dir_el1, x1 +[^:]*: d538cb60 mrs x0, icc_rpr_el1 +[^:]*: d518cba1 msr icc_sgi1r_el1, x1 +[^:]*: d518cbc1 msr icc_asgi1r_el1, x1 +[^:]*: d518cbe1 msr icc_sgi0r_el1, x1 +[^:]*: d538cc00 mrs x0, icc_iar1_el1 +[^:]*: d518cc21 msr icc_eoir1_el1, x1 +[^:]*: d538cc40 mrs x0, icc_hppir1_el1 +[^:]*: d538cc62 mrs x2, icc_bpr1_el1 +[^:]*: d518cc63 msr icc_bpr1_el1, x3 +[^:]*: d538cc82 mrs x2, icc_ctlr_el1 +[^:]*: d518cc83 msr icc_ctlr_el1, x3 +[^:]*: d538ccc2 mrs x2, icc_igrpen0_el1 +[^:]*: d518ccc3 msr icc_igrpen0_el1, x3 +[^:]*: d538cce2 mrs x2, icc_igrpen1_el1 +[^:]*: d518cce3 msr icc_igrpen1_el1, x3 +[^:]*: d53cc802 mrs x2, ich_ap0r0_el2 +[^:]*: d51cc803 msr ich_ap0r0_el2, x3 +[^:]*: d53cc822 mrs x2, ich_ap0r1_el2 +[^:]*: d51cc823 msr ich_ap0r1_el2, x3 +[^:]*: d53cc842 mrs x2, ich_ap0r2_el2 +[^:]*: d51cc843 msr ich_ap0r2_el2, x3 +[^:]*: d53cc862 mrs x2, ich_ap0r3_el2 +[^:]*: d51cc863 msr ich_ap0r3_el2, x3 +[^:]*: d53cc902 mrs x2, ich_ap1r0_el2 +[^:]*: d51cc903 msr ich_ap1r0_el2, x3 +[^:]*: d53cc922 mrs x2, ich_ap1r1_el2 +[^:]*: d51cc923 msr ich_ap1r1_el2, x3 +[^:]*: d53cc942 mrs x2, ich_ap1r2_el2 +[^:]*: d51cc943 msr ich_ap1r2_el2, x3 +[^:]*: d53cc962 mrs x2, ich_ap1r3_el2 +[^:]*: d51cc963 msr ich_ap1r3_el2, x3 +[^:]*: d53ccb02 mrs x2, ich_hcr_el2 +[^:]*: d51ccb03 msr ich_hcr_el2, x3 +[^:]*: d53ccb40 mrs x0, ich_misr_el2 +[^:]*: d53ccb60 mrs x0, ich_eisr_el2 +[^:]*: d53ccba0 mrs x0, ich_elrsr_el2 +[^:]*: d53ccbe2 mrs x2, ich_vmcr_el2 +[^:]*: d51ccbe3 msr ich_vmcr_el2, x3 +[^:]*: d53ccc02 mrs x2, ich_lr0_el2 +[^:]*: d51ccc03 msr ich_lr0_el2, x3 +[^:]*: d53ccc22 mrs x2, ich_lr1_el2 +[^:]*: d51ccc23 msr ich_lr1_el2, x3 +[^:]*: d53ccc42 mrs x2, ich_lr2_el2 +[^:]*: d51ccc43 msr ich_lr2_el2, x3 +[^:]*: d53ccc62 mrs x2, ich_lr3_el2 +[^:]*: d51ccc63 msr ich_lr3_el2, x3 +[^:]*: d53ccc82 mrs x2, ich_lr4_el2 +[^:]*: d51ccc83 msr ich_lr4_el2, x3 +[^:]*: d53ccca2 mrs x2, ich_lr5_el2 +[^:]*: d51ccca3 msr ich_lr5_el2, x3 +[^:]*: d53cccc2 mrs x2, ich_lr6_el2 +[^:]*: d51cccc3 msr ich_lr6_el2, x3 +[^:]*: d53ccce2 mrs x2, ich_lr7_el2 +[^:]*: d51ccce3 msr ich_lr7_el2, x3 +[^:]*: d53ccd02 mrs x2, ich_lr8_el2 +[^:]*: d51ccd03 msr ich_lr8_el2, x3 +[^:]*: d53ccd22 mrs x2, ich_lr9_el2 +[^:]*: d51ccd23 msr ich_lr9_el2, x3 +[^:]*: d53ccd42 mrs x2, ich_lr10_el2 +[^:]*: d51ccd43 msr ich_lr10_el2, x3 +[^:]*: d53ccd62 mrs x2, ich_lr11_el2 +[^:]*: d51ccd63 msr ich_lr11_el2, x3 +[^:]*: d53ccd82 mrs x2, ich_lr12_el2 +[^:]*: d51ccd83 msr ich_lr12_el2, x3 +[^:]*: d53ccda2 mrs x2, ich_lr13_el2 +[^:]*: d51ccda3 msr ich_lr13_el2, x3 +[^:]*: d53ccdc2 mrs x2, ich_lr14_el2 +[^:]*: d51ccdc3 msr ich_lr14_el2, x3 +[^:]*: d53ccde2 mrs x2, ich_lr15_el2 +[^:]*: d51ccde3 msr ich_lr15_el2, x3 +[^:]*: d53ecce2 mrs x2, icc_igrpen1_el3 +[^:]*: d51ecce3 msr icc_igrpen1_el3, x3 +[^:]*: d538a4e0 mrs x0, lorid_el1 +[^:]*: d5390040 mrs x0, ccsidr2_el1 +[^:]*: d5381222 mrs x2, trfcr_el1 +[^:]*: d5181223 msr trfcr_el1, x3 +[^:]*: d5389ec0 mrs x0, pmmir_el1 +[^:]*: d53c1222 mrs x2, trfcr_el2 +[^:]*: d51c1223 msr trfcr_el2, x3 +[^:]*: d53d1222 mrs x2, trfcr_el12 +[^:]*: d51d1223 msr trfcr_el12, x3 +[^:]*: d53bd202 mrs x2, amcr_el0 +[^:]*: d51bd203 msr amcr_el0, x3 +[^:]*: d53bd220 mrs x0, amcfgr_el0 +[^:]*: d53bd240 mrs x0, amcgcr_el0 +[^:]*: d53bd262 mrs x2, amuserenr_el0 +[^:]*: d51bd263 msr amuserenr_el0, x3 +[^:]*: d53bd282 mrs x2, amcntenclr0_el0 +[^:]*: d51bd283 msr amcntenclr0_el0, x3 +[^:]*: d53bd2a2 mrs x2, amcntenset0_el0 +[^:]*: d51bd2a3 msr amcntenset0_el0, x3 +[^:]*: d53bd302 mrs x2, amcntenclr1_el0 +[^:]*: d51bd303 msr amcntenclr1_el0, x3 +[^:]*: d53bd322 mrs x2, amcntenset1_el0 +[^:]*: d51bd323 msr amcntenset1_el0, x3 +[^:]*: d53bd402 mrs x2, amevcntr00_el0 +[^:]*: d51bd403 msr amevcntr00_el0, x3 +[^:]*: d53bd422 mrs x2, amevcntr01_el0 +[^:]*: d51bd423 msr amevcntr01_el0, x3 +[^:]*: d53bd442 mrs x2, amevcntr02_el0 +[^:]*: d51bd443 msr amevcntr02_el0, x3 +[^:]*: d53bd462 mrs x2, amevcntr03_el0 +[^:]*: d51bd463 msr amevcntr03_el0, x3 +[^:]*: d53bd600 mrs x0, amevtyper00_el0 +[^:]*: d53bd620 mrs x0, amevtyper01_el0 +[^:]*: d53bd640 mrs x0, amevtyper02_el0 +[^:]*: d53bd660 mrs x0, amevtyper03_el0 +[^:]*: d53bdc02 mrs x2, amevcntr10_el0 +[^:]*: d51bdc03 msr amevcntr10_el0, x3 +[^:]*: d53bdc22 mrs x2, amevcntr11_el0 +[^:]*: d51bdc23 msr amevcntr11_el0, x3 +[^:]*: d53bdc42 mrs x2, amevcntr12_el0 +[^:]*: d51bdc43 msr amevcntr12_el0, x3 +[^:]*: d53bdc62 mrs x2, amevcntr13_el0 +[^:]*: d51bdc63 msr amevcntr13_el0, x3 +[^:]*: d53bdc82 mrs x2, amevcntr14_el0 +[^:]*: d51bdc83 msr amevcntr14_el0, x3 +[^:]*: d53bdca2 mrs x2, amevcntr15_el0 +[^:]*: d51bdca3 msr amevcntr15_el0, x3 +[^:]*: d53bdcc2 mrs x2, amevcntr16_el0 +[^:]*: d51bdcc3 msr amevcntr16_el0, x3 +[^:]*: d53bdce2 mrs x2, amevcntr17_el0 +[^:]*: d51bdce3 msr amevcntr17_el0, x3 +[^:]*: d53bdd02 mrs x2, amevcntr18_el0 +[^:]*: d51bdd03 msr amevcntr18_el0, x3 +[^:]*: d53bdd22 mrs x2, amevcntr19_el0 +[^:]*: d51bdd23 msr amevcntr19_el0, x3 +[^:]*: d53bdd42 mrs x2, amevcntr110_el0 +[^:]*: d51bdd43 msr amevcntr110_el0, x3 +[^:]*: d53bdd62 mrs x2, amevcntr111_el0 +[^:]*: d51bdd63 msr amevcntr111_el0, x3 +[^:]*: d53bdd82 mrs x2, amevcntr112_el0 +[^:]*: d51bdd83 msr amevcntr112_el0, x3 +[^:]*: d53bdda2 mrs x2, amevcntr113_el0 +[^:]*: d51bdda3 msr amevcntr113_el0, x3 +[^:]*: d53bddc2 mrs x2, amevcntr114_el0 +[^:]*: d51bddc3 msr amevcntr114_el0, x3 +[^:]*: d53bdde2 mrs x2, amevcntr115_el0 +[^:]*: d51bdde3 msr amevcntr115_el0, x3 +[^:]*: d53bde02 mrs x2, amevtyper10_el0 +[^:]*: d51bde03 msr amevtyper10_el0, x3 +[^:]*: d53bde22 mrs x2, amevtyper11_el0 +[^:]*: d51bde23 msr amevtyper11_el0, x3 +[^:]*: d53bde42 mrs x2, amevtyper12_el0 +[^:]*: d51bde43 msr amevtyper12_el0, x3 +[^:]*: d53bde62 mrs x2, amevtyper13_el0 +[^:]*: d51bde63 msr amevtyper13_el0, x3 +[^:]*: d53bde82 mrs x2, amevtyper14_el0 +[^:]*: d51bde83 msr amevtyper14_el0, x3 +[^:]*: d53bdea2 mrs x2, amevtyper15_el0 +[^:]*: d51bdea3 msr amevtyper15_el0, x3 +[^:]*: d53bdec2 mrs x2, amevtyper16_el0 +[^:]*: d51bdec3 msr amevtyper16_el0, x3 +[^:]*: d53bdee2 mrs x2, amevtyper17_el0 +[^:]*: d51bdee3 msr amevtyper17_el0, x3 +[^:]*: d53bdf02 mrs x2, amevtyper18_el0 +[^:]*: d51bdf03 msr amevtyper18_el0, x3 +[^:]*: d53bdf22 mrs x2, amevtyper19_el0 +[^:]*: d51bdf23 msr amevtyper19_el0, x3 +[^:]*: d53bdf42 mrs x2, amevtyper110_el0 +[^:]*: d51bdf43 msr amevtyper110_el0, x3 +[^:]*: d53bdf62 mrs x2, amevtyper111_el0 +[^:]*: d51bdf63 msr amevtyper111_el0, x3 +[^:]*: d53bdf82 mrs x2, amevtyper112_el0 +[^:]*: d51bdf83 msr amevtyper112_el0, x3 +[^:]*: d53bdfa2 mrs x2, amevtyper113_el0 +[^:]*: d51bdfa3 msr amevtyper113_el0, x3 +[^:]*: d53bdfc2 mrs x2, amevtyper114_el0 +[^:]*: d51bdfc3 msr amevtyper114_el0, x3 +[^:]*: d53bdfe2 mrs x2, amevtyper115_el0 +[^:]*: d51bdfe3 msr amevtyper115_el0, x3 +[^:]*: d53bd2c0 mrs x0, amcg1idr_el0 +[^:]*: d53be0a0 mrs x0, cntpctss_el0 +[^:]*: d53be0c0 mrs x0, cntvctss_el0 +[^:]*: d53c1182 mrs x2, hfgrtr_el2 +[^:]*: d51c1183 msr hfgrtr_el2, x3 +[^:]*: d53c11a2 mrs x2, hfgwtr_el2 +[^:]*: d51c11a3 msr hfgwtr_el2, x3 +[^:]*: d53c11c2 mrs x2, hfgitr_el2 +[^:]*: d51c11c3 msr hfgitr_el2, x3 +[^:]*: d53c3182 mrs x2, hdfgrtr_el2 +[^:]*: d51c3183 msr hdfgrtr_el2, x3 +[^:]*: d53c31a2 mrs x2, hdfgwtr_el2 +[^:]*: d51c31a3 msr hdfgwtr_el2, x3 +[^:]*: d53c31c2 mrs x2, hafgrtr_el2 +[^:]*: d51c31c3 msr hafgrtr_el2, x3 +[^:]*: d53cd802 mrs x2, amevcntvoff00_el2 +[^:]*: d51cd803 msr amevcntvoff00_el2, x3 +[^:]*: d53cd822 mrs x2, amevcntvoff01_el2 +[^:]*: d51cd823 msr amevcntvoff01_el2, x3 +[^:]*: d53cd842 mrs x2, amevcntvoff02_el2 +[^:]*: d51cd843 msr amevcntvoff02_el2, x3 +[^:]*: d53cd862 mrs x2, amevcntvoff03_el2 +[^:]*: d51cd863 msr amevcntvoff03_el2, x3 +[^:]*: d53cd882 mrs x2, amevcntvoff04_el2 +[^:]*: d51cd883 msr amevcntvoff04_el2, x3 +[^:]*: d53cd8a2 mrs x2, amevcntvoff05_el2 +[^:]*: d51cd8a3 msr amevcntvoff05_el2, x3 +[^:]*: d53cd8c2 mrs x2, amevcntvoff06_el2 +[^:]*: d51cd8c3 msr amevcntvoff06_el2, x3 +[^:]*: d53cd8e2 mrs x2, amevcntvoff07_el2 +[^:]*: d51cd8e3 msr amevcntvoff07_el2, x3 +[^:]*: d53cd902 mrs x2, amevcntvoff08_el2 +[^:]*: d51cd903 msr amevcntvoff08_el2, x3 +[^:]*: d53cd922 mrs x2, amevcntvoff09_el2 +[^:]*: d51cd923 msr amevcntvoff09_el2, x3 +[^:]*: d53cd942 mrs x2, amevcntvoff010_el2 +[^:]*: d51cd943 msr amevcntvoff010_el2, x3 +[^:]*: d53cd962 mrs x2, amevcntvoff011_el2 +[^:]*: d51cd963 msr amevcntvoff011_el2, x3 +[^:]*: d53cd982 mrs x2, amevcntvoff012_el2 +[^:]*: d51cd983 msr amevcntvoff012_el2, x3 +[^:]*: d53cd9a2 mrs x2, amevcntvoff013_el2 +[^:]*: d51cd9a3 msr amevcntvoff013_el2, x3 +[^:]*: d53cd9c2 mrs x2, amevcntvoff014_el2 +[^:]*: d51cd9c3 msr amevcntvoff014_el2, x3 +[^:]*: d53cd9e2 mrs x2, amevcntvoff015_el2 +[^:]*: d51cd9e3 msr amevcntvoff015_el2, x3 +[^:]*: d53cda02 mrs x2, amevcntvoff10_el2 +[^:]*: d51cda03 msr amevcntvoff10_el2, x3 +[^:]*: d53cda22 mrs x2, amevcntvoff11_el2 +[^:]*: d51cda23 msr amevcntvoff11_el2, x3 +[^:]*: d53cda42 mrs x2, amevcntvoff12_el2 +[^:]*: d51cda43 msr amevcntvoff12_el2, x3 +[^:]*: d53cda62 mrs x2, amevcntvoff13_el2 +[^:]*: d51cda63 msr amevcntvoff13_el2, x3 +[^:]*: d53cda82 mrs x2, amevcntvoff14_el2 +[^:]*: d51cda83 msr amevcntvoff14_el2, x3 +[^:]*: d53cdaa2 mrs x2, amevcntvoff15_el2 +[^:]*: d51cdaa3 msr amevcntvoff15_el2, x3 +[^:]*: d53cdac2 mrs x2, amevcntvoff16_el2 +[^:]*: d51cdac3 msr amevcntvoff16_el2, x3 +[^:]*: d53cdae2 mrs x2, amevcntvoff17_el2 +[^:]*: d51cdae3 msr amevcntvoff17_el2, x3 +[^:]*: d53cdb02 mrs x2, amevcntvoff18_el2 +[^:]*: d51cdb03 msr amevcntvoff18_el2, x3 +[^:]*: d53cdb22 mrs x2, amevcntvoff19_el2 +[^:]*: d51cdb23 msr amevcntvoff19_el2, x3 +[^:]*: d53cdb42 mrs x2, amevcntvoff110_el2 +[^:]*: d51cdb43 msr amevcntvoff110_el2, x3 +[^:]*: d53cdb62 mrs x2, amevcntvoff111_el2 +[^:]*: d51cdb63 msr amevcntvoff111_el2, x3 +[^:]*: d53cdb82 mrs x2, amevcntvoff112_el2 +[^:]*: d51cdb83 msr amevcntvoff112_el2, x3 +[^:]*: d53cdba2 mrs x2, amevcntvoff113_el2 +[^:]*: d51cdba3 msr amevcntvoff113_el2, x3 +[^:]*: d53cdbc2 mrs x2, amevcntvoff114_el2 +[^:]*: d51cdbc3 msr amevcntvoff114_el2, x3 +[^:]*: d53cdbe2 mrs x2, amevcntvoff115_el2 +[^:]*: d51cdbe3 msr amevcntvoff115_el2, x3 +[^:]*: d53ce0c2 mrs x2, cntpoff_el2 +[^:]*: d51ce0c3 msr cntpoff_el2, x3 +[^:]*: d5389922 mrs x2, pmsnevfr_el1 +[^:]*: d5189923 msr pmsnevfr_el1, x3 +[^:]*: d53c1242 mrs x2, hcrx_el2 +[^:]*: d51c1243 msr hcrx_el2, x3 diff --git a/gas/testsuite/gas/aarch64/sysreg-8.s b/gas/testsuite/gas/aarch64/sysreg-8.s new file mode 100644 index 00000000000..8ce36c7c7a0 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sysreg-8.s @@ -0,0 +1,187 @@ + .macro roreg, name + mrs x0, \name + .endm + + .macro woreg, name + msr \name, x1 + .endm + + .macro rwreg, name + mrs x2, \name + msr \name, x3 + .endm + + roreg id_dfr1_el1 + roreg id_mmfr5_el1 + roreg id_isar6_el1 + + rwreg icc_pmr_el1 + roreg icc_iar0_el1 + woreg icc_eoir0_el1 + roreg icc_hppir0_el1 + rwreg icc_bpr0_el1 + rwreg icc_ap0r0_el1 + rwreg icc_ap0r1_el1 + rwreg icc_ap0r2_el1 + rwreg icc_ap0r3_el1 + rwreg icc_ap1r0_el1 + rwreg icc_ap1r1_el1 + rwreg icc_ap1r2_el1 + rwreg icc_ap1r3_el1 + woreg icc_dir_el1 + roreg icc_rpr_el1 + woreg icc_sgi1r_el1 + woreg icc_asgi1r_el1 + woreg icc_sgi0r_el1 + roreg icc_iar1_el1 + woreg icc_eoir1_el1 + roreg icc_hppir1_el1 + rwreg icc_bpr1_el1 + rwreg icc_ctlr_el1 + rwreg icc_igrpen0_el1 + rwreg icc_igrpen1_el1 + rwreg ich_ap0r0_el2 + rwreg ich_ap0r1_el2 + rwreg ich_ap0r2_el2 + rwreg ich_ap0r3_el2 + rwreg ich_ap1r0_el2 + rwreg ich_ap1r1_el2 + rwreg ich_ap1r2_el2 + rwreg ich_ap1r3_el2 + rwreg ich_hcr_el2 + roreg ich_misr_el2 + roreg ich_eisr_el2 + roreg ich_elrsr_el2 + rwreg ich_vmcr_el2 + rwreg ich_lr0_el2 + rwreg ich_lr1_el2 + rwreg ich_lr2_el2 + rwreg ich_lr3_el2 + rwreg ich_lr4_el2 + rwreg ich_lr5_el2 + rwreg ich_lr6_el2 + rwreg ich_lr7_el2 + rwreg ich_lr8_el2 + rwreg ich_lr9_el2 + rwreg ich_lr10_el2 + rwreg ich_lr11_el2 + rwreg ich_lr12_el2 + rwreg ich_lr13_el2 + rwreg ich_lr14_el2 + rwreg ich_lr15_el2 + rwreg icc_igrpen1_el3 + + .arch armv8.1-a + + roreg lorid_el1 + + .arch armv8.3-a + + roreg ccsidr2_el1 + + .arch armv8.4-a + + rwreg trfcr_el1 + roreg pmmir_el1 + rwreg trfcr_el2 + + rwreg trfcr_el12 + + rwreg amcr_el0 + roreg amcfgr_el0 + roreg amcgcr_el0 + rwreg amuserenr_el0 + rwreg amcntenclr0_el0 + rwreg amcntenset0_el0 + rwreg amcntenclr1_el0 + rwreg amcntenset1_el0 + rwreg amevcntr00_el0 + rwreg amevcntr01_el0 + rwreg amevcntr02_el0 + rwreg amevcntr03_el0 + roreg amevtyper00_el0 + roreg amevtyper01_el0 + roreg amevtyper02_el0 + roreg amevtyper03_el0 + rwreg amevcntr10_el0 + rwreg amevcntr11_el0 + rwreg amevcntr12_el0 + rwreg amevcntr13_el0 + rwreg amevcntr14_el0 + rwreg amevcntr15_el0 + rwreg amevcntr16_el0 + rwreg amevcntr17_el0 + rwreg amevcntr18_el0 + rwreg amevcntr19_el0 + rwreg amevcntr110_el0 + rwreg amevcntr111_el0 + rwreg amevcntr112_el0 + rwreg amevcntr113_el0 + rwreg amevcntr114_el0 + rwreg amevcntr115_el0 + rwreg amevtyper10_el0 + rwreg amevtyper11_el0 + rwreg amevtyper12_el0 + rwreg amevtyper13_el0 + rwreg amevtyper14_el0 + rwreg amevtyper15_el0 + rwreg amevtyper16_el0 + rwreg amevtyper17_el0 + rwreg amevtyper18_el0 + rwreg amevtyper19_el0 + rwreg amevtyper110_el0 + rwreg amevtyper111_el0 + rwreg amevtyper112_el0 + rwreg amevtyper113_el0 + rwreg amevtyper114_el0 + rwreg amevtyper115_el0 + + .arch armv8.6-a + + roreg amcg1idr_el0 + roreg cntpctss_el0 + roreg cntvctss_el0 + rwreg hfgrtr_el2 + rwreg hfgwtr_el2 + rwreg hfgitr_el2 + rwreg hdfgrtr_el2 + rwreg hdfgwtr_el2 + rwreg hafgrtr_el2 + rwreg amevcntvoff00_el2 + rwreg amevcntvoff01_el2 + rwreg amevcntvoff02_el2 + rwreg amevcntvoff03_el2 + rwreg amevcntvoff04_el2 + rwreg amevcntvoff05_el2 + rwreg amevcntvoff06_el2 + rwreg amevcntvoff07_el2 + rwreg amevcntvoff08_el2 + rwreg amevcntvoff09_el2 + rwreg amevcntvoff010_el2 + rwreg amevcntvoff011_el2 + rwreg amevcntvoff012_el2 + rwreg amevcntvoff013_el2 + rwreg amevcntvoff014_el2 + rwreg amevcntvoff015_el2 + rwreg amevcntvoff10_el2 + rwreg amevcntvoff11_el2 + rwreg amevcntvoff12_el2 + rwreg amevcntvoff13_el2 + rwreg amevcntvoff14_el2 + rwreg amevcntvoff15_el2 + rwreg amevcntvoff16_el2 + rwreg amevcntvoff17_el2 + rwreg amevcntvoff18_el2 + rwreg amevcntvoff19_el2 + rwreg amevcntvoff110_el2 + rwreg amevcntvoff111_el2 + rwreg amevcntvoff112_el2 + rwreg amevcntvoff113_el2 + rwreg amevcntvoff114_el2 + rwreg amevcntvoff115_el2 + rwreg cntpoff_el2 + + .arch armv8.7-a + + rwreg pmsnevfr_el1 + rwreg hcrx_el2 diff --git a/gas/testsuite/gas/aarch64/sysreg.d b/gas/testsuite/gas/aarch64/sysreg.d index 35b829e0dd3..5da20c99847 100644 --- a/gas/testsuite/gas/aarch64/sysreg.d +++ b/gas/testsuite/gas/aarch64/sysreg.d @@ -24,8 +24,8 @@ Disassembly of section \.text: 40: d5380260 mrs x0, id_isar3_el1 44: d5380280 mrs x0, id_isar4_el1 48: d53802a0 mrs x0, id_isar5_el1 - 4c: d538cc00 mrs x0, s3_0_c12_c12_0 - 50: d5384600 mrs x0, s3_0_c4_c6_0 - 54: d5184600 msr s3_0_c4_c6_0, x0 + 4c: d538cf00 mrs x0, s3_0_c12_c15_0 + 50: d5384b00 mrs x0, s3_0_c4_c11_0 + 54: d5184b00 msr s3_0_c4_c11_0, x0 58: d5310300 mrs x0, trcstatr 5c: d5110300 msr trcstatr, x0 diff --git a/gas/testsuite/gas/aarch64/sysreg.s b/gas/testsuite/gas/aarch64/sysreg.s index 897467409c4..fa797284f23 100644 --- a/gas/testsuite/gas/aarch64/sysreg.s +++ b/gas/testsuite/gas/aarch64/sysreg.s @@ -24,9 +24,9 @@ mrs x0, id_isar4_el1 mrs x0, id_isar5_el1 - mrs x0, s3_0_c12_c12_0 - mrs x0, s3_0_c4_c6_0 - msr s3_0_c4_c6_0, x0 + mrs x0, s3_0_c12_c15_0 + mrs x0, s3_0_c4_c11_0 + msr s3_0_c4_c11_0, x0 mrs x0, s2_1_c0_c3_0 msr s2_1_c0_c3_0, x0 diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index a0959155787..25f96c687a4 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -3989,7 +3989,12 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, #define SR_V8_2(n,e,f) SR_FEAT (n,e,f,V8_2) #define SR_V8_3(n,e,f) SR_FEAT (n,e,f,V8_3) #define SR_V8_4(n,e,f) SR_FEAT (n,e,f,V8_4) -#define SR_V8_4(n,e,f) SR_FEAT (n,e,f,V8_4) +#define SR_V8_6(n,e,f) SR_FEAT (n,e,f,V8_6) +#define SR_V8_7(n,e,f) SR_FEAT (n,e,f,V8_7) +/* Has no separate libopcodes feature flag, but separated out for clarity. */ +#define SR_GIC(n,e,f) SR_CORE (n,e,f) +/* Has no separate libopcodes feature flag, but separated out for clarity. */ +#define SR_AMU(n,e,f) SR_FEAT (n,e,f,V8_4) #define SR_LOR(n,e,f) SR_FEAT (n,e,f,LOR) #define SR_PAN(n,e,f) SR_FEAT (n,e,f,PAN) #define SR_RAS(n,e,f) SR_FEAT (n,e,f,RAS) @@ -4064,6 +4069,7 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_CORE ("aidr_el1", CPENC (3,1,C0,C0,7), F_REG_READ), SR_CORE ("dczid_el0", CPENC (3,3,C0,C0,7), F_REG_READ), SR_CORE ("id_dfr0_el1", CPENC (3,0,C0,C1,2), F_REG_READ), + SR_CORE ("id_dfr1_el1", CPENC (3,0,C0,C3,5), F_REG_READ), SR_CORE ("id_pfr0_el1", CPENC (3,0,C0,C1,0), F_REG_READ), SR_CORE ("id_pfr1_el1", CPENC (3,0,C0,C1,1), F_REG_READ), SR_ID_PFR2 ("id_pfr2_el1", CPENC (3,0,C0,C3,4), F_REG_READ), @@ -4073,16 +4079,19 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_CORE ("id_mmfr2_el1", CPENC (3,0,C0,C1,6), F_REG_READ), SR_CORE ("id_mmfr3_el1", CPENC (3,0,C0,C1,7), F_REG_READ), SR_CORE ("id_mmfr4_el1", CPENC (3,0,C0,C2,6), F_REG_READ), + SR_CORE ("id_mmfr5_el1", CPENC (3,0,C0,C3,6), F_REG_READ), SR_CORE ("id_isar0_el1", CPENC (3,0,C0,C2,0), F_REG_READ), SR_CORE ("id_isar1_el1", CPENC (3,0,C0,C2,1), F_REG_READ), SR_CORE ("id_isar2_el1", CPENC (3,0,C0,C2,2), F_REG_READ), SR_CORE ("id_isar3_el1", CPENC (3,0,C0,C2,3), F_REG_READ), SR_CORE ("id_isar4_el1", CPENC (3,0,C0,C2,4), F_REG_READ), SR_CORE ("id_isar5_el1", CPENC (3,0,C0,C2,5), F_REG_READ), + SR_CORE ("id_isar6_el1", CPENC (3,0,C0,C2,7), F_REG_READ), SR_CORE ("mvfr0_el1", CPENC (3,0,C0,C3,0), F_REG_READ), SR_CORE ("mvfr1_el1", CPENC (3,0,C0,C3,1), F_REG_READ), SR_CORE ("mvfr2_el1", CPENC (3,0,C0,C3,2), F_REG_READ), SR_CORE ("ccsidr_el1", CPENC (3,1,C0,C0,0), F_REG_READ), + SR_V8_3 ("ccsidr2_el1", CPENC (3,1,C0,C0,2), F_REG_READ), SR_CORE ("id_aa64pfr0_el1", CPENC (3,0,C0,C4,0), F_REG_READ), SR_CORE ("id_aa64pfr1_el1", CPENC (3,0,C0,C4,1), F_REG_READ), SR_CORE ("id_aa64dfr0_el1", CPENC (3,0,C0,C5,0), F_REG_READ), @@ -4429,6 +4438,9 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_CORE ("pmccfiltr_el0", CPENC (3,3,C14,C15,7), 0), SR_V8_4 ("dit", CPEN_ (3,C2,5), 0), + SR_V8_4 ("trfcr_el1", CPENC (3,0,C1,C2,1), 0), + SR_V8_4 ("pmmir_el1", CPENC (3,0,C9,C14,6), F_REG_READ), + SR_V8_4 ("trfcr_el2", CPENC (3,4,C1,C2,1), 0), SR_V8_4 ("vstcr_el2", CPENC (3,4,C2,C6,2), 0), SR_V8_4_A ("vsttbr_el2", CPENC (3,4,C2,C6,0), 0), SR_V8_4 ("cnthvs_tval_el2", CPENC (3,4,C14,C4,0), 0), @@ -4439,6 +4451,7 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_V8_4 ("cnthps_ctl_el2", CPENC (3,4,C14,C5,1), 0), SR_V8_4 ("sder32_el2", CPENC (3,4,C1,C3,1), 0), SR_V8_4 ("vncr_el2", CPENC (3,4,C2,C2,0), 0), + SR_V8_4 ("trfcr_el12", CPENC (3,5,C1,C2,1), 0), SR_CORE ("mpam0_el1", CPENC (3,0,C10,C5,1), 0), SR_CORE ("mpam1_el1", CPENC (3,0,C10,C5,0), 0), @@ -4715,6 +4728,7 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_CORE ("csrptr_el2", CPENC (2,4,C8,C0,1), 0), SR_CORE ("csrptridx_el2", CPENC (2,4,C8,C0,3), F_REG_READ), + SR_LOR ("lorid_el1", CPENC (3,0,C10,C4,7), F_REG_READ), SR_LOR ("lorc_el1", CPENC (3,0,C10,C4,3), 0), SR_LOR ("lorea_el1", CPENC (3,0,C10,C4,1), 0), SR_LOR ("lorn_el1", CPENC (3,0,C10,C4,2), 0), @@ -4850,6 +4864,157 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_SME ("tpidr2_el0", CPENC (3,3,C13,C0,5), 0), SR_SME ("mpamsm_el1", CPENC (3,0,C10,C5,3), 0), + SR_AMU ("amcr_el0", CPENC (3,3,C13,C2,0), 0), + SR_AMU ("amcfgr_el0", CPENC (3,3,C13,C2,1), F_REG_READ), + SR_AMU ("amcgcr_el0", CPENC (3,3,C13,C2,2), F_REG_READ), + SR_AMU ("amuserenr_el0", CPENC (3,3,C13,C2,3), 0), + SR_AMU ("amcntenclr0_el0", CPENC (3,3,C13,C2,4), 0), + SR_AMU ("amcntenset0_el0", CPENC (3,3,C13,C2,5), 0), + SR_AMU ("amcntenclr1_el0", CPENC (3,3,C13,C3,0), 0), + SR_AMU ("amcntenset1_el0", CPENC (3,3,C13,C3,1), 0), + SR_AMU ("amevcntr00_el0", CPENC (3,3,C13,C4,0), 0), + SR_AMU ("amevcntr01_el0", CPENC (3,3,C13,C4,1), 0), + SR_AMU ("amevcntr02_el0", CPENC (3,3,C13,C4,2), 0), + SR_AMU ("amevcntr03_el0", CPENC (3,3,C13,C4,3), 0), + SR_AMU ("amevtyper00_el0", CPENC (3,3,C13,C6,0), F_REG_READ), + SR_AMU ("amevtyper01_el0", CPENC (3,3,C13,C6,1), F_REG_READ), + SR_AMU ("amevtyper02_el0", CPENC (3,3,C13,C6,2), F_REG_READ), + SR_AMU ("amevtyper03_el0", CPENC (3,3,C13,C6,3), F_REG_READ), + SR_AMU ("amevcntr10_el0", CPENC (3,3,C13,C12,0), 0), + SR_AMU ("amevcntr11_el0", CPENC (3,3,C13,C12,1), 0), + SR_AMU ("amevcntr12_el0", CPENC (3,3,C13,C12,2), 0), + SR_AMU ("amevcntr13_el0", CPENC (3,3,C13,C12,3), 0), + SR_AMU ("amevcntr14_el0", CPENC (3,3,C13,C12,4), 0), + SR_AMU ("amevcntr15_el0", CPENC (3,3,C13,C12,5), 0), + SR_AMU ("amevcntr16_el0", CPENC (3,3,C13,C12,6), 0), + SR_AMU ("amevcntr17_el0", CPENC (3,3,C13,C12,7), 0), + SR_AMU ("amevcntr18_el0", CPENC (3,3,C13,C13,0), 0), + SR_AMU ("amevcntr19_el0", CPENC (3,3,C13,C13,1), 0), + SR_AMU ("amevcntr110_el0", CPENC (3,3,C13,C13,2), 0), + SR_AMU ("amevcntr111_el0", CPENC (3,3,C13,C13,3), 0), + SR_AMU ("amevcntr112_el0", CPENC (3,3,C13,C13,4), 0), + SR_AMU ("amevcntr113_el0", CPENC (3,3,C13,C13,5), 0), + SR_AMU ("amevcntr114_el0", CPENC (3,3,C13,C13,6), 0), + SR_AMU ("amevcntr115_el0", CPENC (3,3,C13,C13,7), 0), + SR_AMU ("amevtyper10_el0", CPENC (3,3,C13,C14,0), 0), + SR_AMU ("amevtyper11_el0", CPENC (3,3,C13,C14,1), 0), + SR_AMU ("amevtyper12_el0", CPENC (3,3,C13,C14,2), 0), + SR_AMU ("amevtyper13_el0", CPENC (3,3,C13,C14,3), 0), + SR_AMU ("amevtyper14_el0", CPENC (3,3,C13,C14,4), 0), + SR_AMU ("amevtyper15_el0", CPENC (3,3,C13,C14,5), 0), + SR_AMU ("amevtyper16_el0", CPENC (3,3,C13,C14,6), 0), + SR_AMU ("amevtyper17_el0", CPENC (3,3,C13,C14,7), 0), + SR_AMU ("amevtyper18_el0", CPENC (3,3,C13,C15,0), 0), + SR_AMU ("amevtyper19_el0", CPENC (3,3,C13,C15,1), 0), + SR_AMU ("amevtyper110_el0", CPENC (3,3,C13,C15,2), 0), + SR_AMU ("amevtyper111_el0", CPENC (3,3,C13,C15,3), 0), + SR_AMU ("amevtyper112_el0", CPENC (3,3,C13,C15,4), 0), + SR_AMU ("amevtyper113_el0", CPENC (3,3,C13,C15,5), 0), + SR_AMU ("amevtyper114_el0", CPENC (3,3,C13,C15,6), 0), + SR_AMU ("amevtyper115_el0", CPENC (3,3,C13,C15,7), 0), + + SR_GIC ("icc_pmr_el1", CPENC (3,0,C4,C6,0), 0), + SR_GIC ("icc_iar0_el1", CPENC (3,0,C12,C8,0), F_REG_READ), + SR_GIC ("icc_eoir0_el1", CPENC (3,0,C12,C8,1), F_REG_WRITE), + SR_GIC ("icc_hppir0_el1", CPENC (3,0,C12,C8,2), F_REG_READ), + SR_GIC ("icc_bpr0_el1", CPENC (3,0,C12,C8,3), 0), + SR_GIC ("icc_ap0r0_el1", CPENC (3,0,C12,C8,4), 0), + SR_GIC ("icc_ap0r1_el1", CPENC (3,0,C12,C8,5), 0), + SR_GIC ("icc_ap0r2_el1", CPENC (3,0,C12,C8,6), 0), + SR_GIC ("icc_ap0r3_el1", CPENC (3,0,C12,C8,7), 0), + SR_GIC ("icc_ap1r0_el1", CPENC (3,0,C12,C9,0), 0), + SR_GIC ("icc_ap1r1_el1", CPENC (3,0,C12,C9,1), 0), + SR_GIC ("icc_ap1r2_el1", CPENC (3,0,C12,C9,2), 0), + SR_GIC ("icc_ap1r3_el1", CPENC (3,0,C12,C9,3), 0), + SR_GIC ("icc_dir_el1", CPENC (3,0,C12,C11,1), F_REG_WRITE), + SR_GIC ("icc_rpr_el1", CPENC (3,0,C12,C11,3), F_REG_READ), + SR_GIC ("icc_sgi1r_el1", CPENC (3,0,C12,C11,5), F_REG_WRITE), + SR_GIC ("icc_asgi1r_el1", CPENC (3,0,C12,C11,6), F_REG_WRITE), + SR_GIC ("icc_sgi0r_el1", CPENC (3,0,C12,C11,7), F_REG_WRITE), + SR_GIC ("icc_iar1_el1", CPENC (3,0,C12,C12,0), F_REG_READ), + SR_GIC ("icc_eoir1_el1", CPENC (3,0,C12,C12,1), F_REG_WRITE), + SR_GIC ("icc_hppir1_el1", CPENC (3,0,C12,C12,2), F_REG_READ), + SR_GIC ("icc_bpr1_el1", CPENC (3,0,C12,C12,3), 0), + SR_GIC ("icc_ctlr_el1", CPENC (3,0,C12,C12,4), 0), + SR_GIC ("icc_igrpen0_el1", CPENC (3,0,C12,C12,6), 0), + SR_GIC ("icc_igrpen1_el1", CPENC (3,0,C12,C12,7), 0), + SR_GIC ("ich_ap0r0_el2", CPENC (3,4,C12,C8,0), 0), + SR_GIC ("ich_ap0r1_el2", CPENC (3,4,C12,C8,1), 0), + SR_GIC ("ich_ap0r2_el2", CPENC (3,4,C12,C8,2), 0), + SR_GIC ("ich_ap0r3_el2", CPENC (3,4,C12,C8,3), 0), + SR_GIC ("ich_ap1r0_el2", CPENC (3,4,C12,C9,0), 0), + SR_GIC ("ich_ap1r1_el2", CPENC (3,4,C12,C9,1), 0), + SR_GIC ("ich_ap1r2_el2", CPENC (3,4,C12,C9,2), 0), + SR_GIC ("ich_ap1r3_el2", CPENC (3,4,C12,C9,3), 0), + SR_GIC ("ich_hcr_el2", CPENC (3,4,C12,C11,0), 0), + SR_GIC ("ich_misr_el2", CPENC (3,4,C12,C11,2), F_REG_READ), + SR_GIC ("ich_eisr_el2", CPENC (3,4,C12,C11,3), F_REG_READ), + SR_GIC ("ich_elrsr_el2", CPENC (3,4,C12,C11,5), F_REG_READ), + SR_GIC ("ich_vmcr_el2", CPENC (3,4,C12,C11,7), 0), + SR_GIC ("ich_lr0_el2", CPENC (3,4,C12,C12,0), 0), + SR_GIC ("ich_lr1_el2", CPENC (3,4,C12,C12,1), 0), + SR_GIC ("ich_lr2_el2", CPENC (3,4,C12,C12,2), 0), + SR_GIC ("ich_lr3_el2", CPENC (3,4,C12,C12,3), 0), + SR_GIC ("ich_lr4_el2", CPENC (3,4,C12,C12,4), 0), + SR_GIC ("ich_lr5_el2", CPENC (3,4,C12,C12,5), 0), + SR_GIC ("ich_lr6_el2", CPENC (3,4,C12,C12,6), 0), + SR_GIC ("ich_lr7_el2", CPENC (3,4,C12,C12,7), 0), + SR_GIC ("ich_lr8_el2", CPENC (3,4,C12,C13,0), 0), + SR_GIC ("ich_lr9_el2", CPENC (3,4,C12,C13,1), 0), + SR_GIC ("ich_lr10_el2", CPENC (3,4,C12,C13,2), 0), + SR_GIC ("ich_lr11_el2", CPENC (3,4,C12,C13,3), 0), + SR_GIC ("ich_lr12_el2", CPENC (3,4,C12,C13,4), 0), + SR_GIC ("ich_lr13_el2", CPENC (3,4,C12,C13,5), 0), + SR_GIC ("ich_lr14_el2", CPENC (3,4,C12,C13,6), 0), + SR_GIC ("ich_lr15_el2", CPENC (3,4,C12,C13,7), 0), + SR_GIC ("icc_igrpen1_el3", CPENC (3,6,C12,C12,7), 0), + + SR_V8_6 ("amcg1idr_el0", CPENC (3,3,C13,C2,6), F_REG_READ), + SR_V8_6 ("cntpctss_el0", CPENC (3,3,C14,C0,5), F_REG_READ), + SR_V8_6 ("cntvctss_el0", CPENC (3,3,C14,C0,6), F_REG_READ), + SR_V8_6 ("hfgrtr_el2", CPENC (3,4,C1,C1,4), 0), + SR_V8_6 ("hfgwtr_el2", CPENC (3,4,C1,C1,5), 0), + SR_V8_6 ("hfgitr_el2", CPENC (3,4,C1,C1,6), 0), + SR_V8_6 ("hdfgrtr_el2", CPENC (3,4,C3,C1,4), 0), + SR_V8_6 ("hdfgwtr_el2", CPENC (3,4,C3,C1,5), 0), + SR_V8_6 ("hafgrtr_el2", CPENC (3,4,C3,C1,6), 0), + SR_V8_6 ("amevcntvoff00_el2", CPENC (3,4,C13,C8,0), 0), + SR_V8_6 ("amevcntvoff01_el2", CPENC (3,4,C13,C8,1), 0), + SR_V8_6 ("amevcntvoff02_el2", CPENC (3,4,C13,C8,2), 0), + SR_V8_6 ("amevcntvoff03_el2", CPENC (3,4,C13,C8,3), 0), + SR_V8_6 ("amevcntvoff04_el2", CPENC (3,4,C13,C8,4), 0), + SR_V8_6 ("amevcntvoff05_el2", CPENC (3,4,C13,C8,5), 0), + SR_V8_6 ("amevcntvoff06_el2", CPENC (3,4,C13,C8,6), 0), + SR_V8_6 ("amevcntvoff07_el2", CPENC (3,4,C13,C8,7), 0), + SR_V8_6 ("amevcntvoff08_el2", CPENC (3,4,C13,C9,0), 0), + SR_V8_6 ("amevcntvoff09_el2", CPENC (3,4,C13,C9,1), 0), + SR_V8_6 ("amevcntvoff010_el2", CPENC (3,4,C13,C9,2), 0), + SR_V8_6 ("amevcntvoff011_el2", CPENC (3,4,C13,C9,3), 0), + SR_V8_6 ("amevcntvoff012_el2", CPENC (3,4,C13,C9,4), 0), + SR_V8_6 ("amevcntvoff013_el2", CPENC (3,4,C13,C9,5), 0), + SR_V8_6 ("amevcntvoff014_el2", CPENC (3,4,C13,C9,6), 0), + SR_V8_6 ("amevcntvoff015_el2", CPENC (3,4,C13,C9,7), 0), + SR_V8_6 ("amevcntvoff10_el2", CPENC (3,4,C13,C10,0), 0), + SR_V8_6 ("amevcntvoff11_el2", CPENC (3,4,C13,C10,1), 0), + SR_V8_6 ("amevcntvoff12_el2", CPENC (3,4,C13,C10,2), 0), + SR_V8_6 ("amevcntvoff13_el2", CPENC (3,4,C13,C10,3), 0), + SR_V8_6 ("amevcntvoff14_el2", CPENC (3,4,C13,C10,4), 0), + SR_V8_6 ("amevcntvoff15_el2", CPENC (3,4,C13,C10,5), 0), + SR_V8_6 ("amevcntvoff16_el2", CPENC (3,4,C13,C10,6), 0), + SR_V8_6 ("amevcntvoff17_el2", CPENC (3,4,C13,C10,7), 0), + SR_V8_6 ("amevcntvoff18_el2", CPENC (3,4,C13,C11,0), 0), + SR_V8_6 ("amevcntvoff19_el2", CPENC (3,4,C13,C11,1), 0), + SR_V8_6 ("amevcntvoff110_el2", CPENC (3,4,C13,C11,2), 0), + SR_V8_6 ("amevcntvoff111_el2", CPENC (3,4,C13,C11,3), 0), + SR_V8_6 ("amevcntvoff112_el2", CPENC (3,4,C13,C11,4), 0), + SR_V8_6 ("amevcntvoff113_el2", CPENC (3,4,C13,C11,5), 0), + SR_V8_6 ("amevcntvoff114_el2", CPENC (3,4,C13,C11,6), 0), + SR_V8_6 ("amevcntvoff115_el2", CPENC (3,4,C13,C11,7), 0), + SR_V8_6 ("cntpoff_el2", CPENC (3,4,C14,C0,6), 0), + + SR_V8_7 ("pmsnevfr_el1", CPENC (3,0,C9,C9,1), 0), + SR_V8_7 ("hcrx_el2", CPENC (3,4,C1,C2,2), 0), + { 0, CPENC (0,0,0,0,0), 0, 0 } };