From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 11 Sep 2019 20:06:49 +0000 (-0700)
Subject: Make unextend a udata
X-Git-Tag: working-ls180~1039^2~129
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e9eb855d38b3bd4d5a61471af49e791be12817ba;p=yosys.git

Make unextend a udata
---

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 6e726d1c2..6998d6e84 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -1,6 +1,6 @@
 pattern xilinx_dsp
 
-state <std::function<SigSpec(const SigSpec&)>> unextend
+udata <std::function<SigSpec(const SigSpec&)>> unextend
 state <SigBit> clock
 state <SigSpec> sigA sigffAcemuxY sigB sigffBcemuxY sigC sigffCcemuxY sigD sigffDcemuxY sigM sigP
 state <IdString> postAddAB postAddMuxAB
@@ -23,7 +23,7 @@ match dsp
 	select dsp->type.in(\DSP48E1)
 endmatch
 
-code unextend sigA sigB sigC sigD sigM
+code sigA sigB sigC sigD sigM
 	unextend = [](const SigSpec &sig) {
 		int i;
 		for (i = GetSize(sig)-1; i > 0; i--)
@@ -396,7 +396,6 @@ endcode
 
 subpattern out_dffe
 arg argD argQ clock
-arg unextend
 
 code
 	dff = nullptr;