From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sun, 29 Sep 2019 14:10:44 +0000 (+0200)
Subject: soc/cores/gpio: uniformize with others cores
X-Git-Tag: 24jan2021_ls180~964
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e9ed4761b53160e4f55319bfe7010b380e202e6b;p=litex.git

soc/cores/gpio: uniformize with others cores
---

diff --git a/litex/soc/cores/gpio.py b/litex/soc/cores/gpio.py
index b4ec50a3..21028898 100644
--- a/litex/soc/cores/gpio.py
+++ b/litex/soc/cores/gpio.py
@@ -6,18 +6,21 @@ from migen.genlib.cdc import MultiReg
 
 from litex.soc.interconnect.csr import *
 
+# GPIO Input ----------------------------------------------------------------------------------------
 
 class GPIOIn(Module, AutoCSR):
     def __init__(self, signal):
         self._in = CSRStatus(len(signal))
         self.specials += MultiReg(signal, self._in.status)
 
+# GPIO Output --------------------------------------------------------------------------------------
 
 class GPIOOut(Module, AutoCSR):
     def __init__(self, signal):
         self._out = CSRStorage(len(signal))
         self.comb += signal.eq(self._out.storage)
 
+# GPIO Input/Output --------------------------------------------------------------------------------
 
 class GPIOInOut(Module):
     def __init__(self, in_signal, out_signal):