From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 16 Feb 2019 09:05:53 +0000 (+0000)
Subject: move normalise_2 to function
X-Git-Tag: ls180-24jan2020~1964
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e9ef7709bf7955693ab4c9ed74e87f81f4f45632;p=ieee754fpu.git

move normalise_2 to function
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index fef643c8..af947149 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -141,6 +141,18 @@ class FPADD:
         with m.Else():
             m.next = next_state
 
+    def normalise_2(self, m, z, of, next_state):
+        with m.If(z.e < z.N126):
+            m.d.sync +=[
+                z.e.eq(z.e + 1),  # INCREASE exponent
+                z.m.eq(z.m >> 1), # shift mantissa DOWN
+                of.guard.eq(z.m[0]),
+                of.round_bit.eq(of.guard),
+                of.sticky.eq(of.sticky | of.round_bit)
+            ]
+        with m.Else():
+            m.next = next_state
+
     def get_fragment(self, platform=None):
         m = Module()
 
@@ -311,16 +323,7 @@ class FPADD:
             #       the extra mantissa bits coming from tot[0..2]
 
             with m.State("normalise_2"):
-                with m.If(z.e < z.N126):
-                    m.d.sync +=[
-                        z.e.eq(z.e + 1),  # INCREASE exponent
-                        z.m.eq(z.m >> 1), # shift mantissa DOWN
-                        of.guard.eq(z.m[0]),
-                        of.round_bit.eq(of.guard),
-                        of.sticky.eq(of.sticky | of.round_bit)
-                    ]
-                with m.Else():
-                    m.next = "round"
+                self.normalise_2(m, z, of, "round")
 
             # ******
             # rounding stage