From: Marcelina Koƛcielnicka Date: Mon, 12 Jul 2021 18:43:09 +0000 (+0200) Subject: backends/verilog: Support meminit with mask. X-Git-Tag: yosys-0.10~82 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e9effd58d24afc8470813aec3028e932ea677aa5;p=yosys.git backends/verilog: Support meminit with mask. --- diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 800865414..b363bc2fe 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -504,9 +504,24 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) int start = init.addr.as_int(); for (int i=0; i