From: Martin Hunt <hunt@redhat.com>
Date: Sat, 7 Sep 1996 00:58:25 +0000 (+0000)
Subject: Fri Sep  6 17:56:17 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ea2155e858687fdef42d6aa0cacb9752d90f089a;p=binutils-gdb.git

Fri Sep  6 17:56:17 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>

	* simops.c (OP_2600, OP_2601): Changed min and max comparisons
	to use signed register values.
---

diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog
index 32381d854e6..57f9f1ae300 100644
--- a/sim/d10v/ChangeLog
+++ b/sim/d10v/ChangeLog
@@ -1,3 +1,8 @@
+Fri Sep  6 17:56:17 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* simops.c (OP_2600, OP_2601): Changed min and max comparisons
+	to use signed register values.
+
 Wed Sep  4 11:35:17 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
 
 	* d10v_sim.h (DEBUG_*): Add bit flags for controlling debug
diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c
index faf7d7da9bf..dc05f5e936c 100644
--- a/sim/d10v/simops.c
+++ b/sim/d10v/simops.c
@@ -1223,7 +1223,7 @@ OP_2600 ()
 {
   trace_input ("max", OP_REG, OP_REG, OP_VOID);
   State.F1 = State.F0;
-  if (State.regs[OP[1]] > State.regs[OP[0]])
+  if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
     {
       State.regs[OP[0]] = State.regs[OP[1]];
       State.F0 = 1;
@@ -1275,7 +1275,7 @@ OP_2601 ()
 {
   trace_input ("min", OP_REG, OP_REG, OP_VOID);
   State.F1 = State.F0;
-  if (State.regs[OP[1]] < State.regs[OP[0]])
+  if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
     {
       State.regs[OP[0]] = State.regs[OP[1]];
       State.F0 = 1;