From: Florent Kermarrec Date: Fri, 19 Dec 2014 21:32:11 +0000 (+0100) Subject: link: add parameter to disable CONT insertion (will ease debug) X-Git-Tag: 24jan2021_ls180~2572^2~90 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ea245542c62615f1999b535d98801e2ffa8444d7;p=litex.git link: add parameter to disable CONT insertion (will ease debug) --- diff --git a/lib/sata/link/__init__.py b/lib/sata/link/__init__.py index 4182643d..535eda49 100644 --- a/lib/sata/link/__init__.py +++ b/lib/sata/link/__init__.py @@ -35,7 +35,7 @@ class SATALinkTX(Module): # inserter CONT and scrambled data between # CONT and next primitive - cont = SATACONTInserter(phy_description(32)) + cont = SATACONTInserter(phy_description(32), disable=True) self.submodules += cont # datas / primitives mux diff --git a/lib/sata/link/cont.py b/lib/sata/link/cont.py index 9553bb40..9ab28e25 100644 --- a/lib/sata/link/cont.py +++ b/lib/sata/link/cont.py @@ -4,75 +4,78 @@ from lib.sata.link.scrambler import Scrambler from migen.genlib.misc import optree class SATACONTInserter(Module): - def __init__(self, description): + def __init__(self, description, disable=False): self.sink = sink = Sink(description) self.source = source = Source(description) ### - counter = Counter(max=4) - self.submodules += counter + if disable: + self.comb += Record.connect(self.sink, self.source) + else: + counter = Counter(max=4) + self.submodules += counter - is_data = Signal() - was_data = Signal() - change = Signal() - self.comb += is_data.eq(sink.charisk == 0) + is_data = Signal() + was_data = Signal() + change = Signal() + self.comb += is_data.eq(sink.charisk == 0) - last_data = Signal(32) - last_primitive = Signal(32) - last_charisk = Signal(4) - self.sync += [ - If(sink.stb & source.ack, - last_data.eq(sink.data), - last_charisk.eq(sink.charisk), - If(~is_data, - last_primitive.eq(sink.data), - ), - was_data.eq(is_data) - ) - ] - was_hold = last_primitive == primitives["HOLD"] + last_data = Signal(32) + last_primitive = Signal(32) + last_charisk = Signal(4) + self.sync += [ + If(sink.stb & source.ack, + last_data.eq(sink.data), + last_charisk.eq(sink.charisk), + If(~is_data, + last_primitive.eq(sink.data), + ), + was_data.eq(is_data) + ) + ] + was_hold = last_primitive == primitives["HOLD"] - self.comb += change.eq( - (sink.data != last_data) | - (sink.charisk != last_charisk) | - is_data - ) + self.comb += change.eq( + (sink.data != last_data) | + (sink.charisk != last_charisk) | + is_data + ) - # scrambler - scrambler = InsertReset(Scrambler()) - self.submodules += scrambler + # scrambler + scrambler = InsertReset(Scrambler()) + self.submodules += scrambler - # Datapath - self.comb += [ - Record.connect(sink, source), - If(sink.stb, - If(~change, - counter.ce.eq(sink.ack & (counter.value !=2)), - # insert CONT - If(counter.value == 1, - source.charisk.eq(0b0001), - source.data.eq(primitives["CONT"]) - # insert scrambled data for EMI - ).Elif(counter.value == 2, - scrambler.ce.eq(sink.ack), - source.charisk.eq(0b0000), - source.data.eq(scrambler.value) - ) - ).Else( - counter.reset.eq(source.ack), - If(counter.value == 2, - # Reinsert last primitive - If(is_data | (~is_data & was_hold), - source.stb.eq(1), - sink.ack.eq(0), + # Datapath + self.comb += [ + Record.connect(sink, source), + If(sink.stb, + If(~change, + counter.ce.eq(sink.ack & (counter.value !=2)), + # insert CONT + If(counter.value == 1, source.charisk.eq(0b0001), - source.data.eq(last_primitive) + source.data.eq(primitives["CONT"]) + # insert scrambled data for EMI + ).Elif(counter.value == 2, + scrambler.ce.eq(sink.ack), + source.charisk.eq(0b0000), + source.data.eq(scrambler.value) + ) + ).Else( + counter.reset.eq(source.ack), + If(counter.value == 2, + # Reinsert last primitive + If(is_data | (~is_data & was_hold), + source.stb.eq(1), + sink.ack.eq(0), + source.charisk.eq(0b0001), + source.data.eq(last_primitive) + ) ) ) ) - ) - ] + ] class SATACONTRemover(Module): def __init__(self, description):