From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 14 Oct 2018 04:42:39 +0000 (+0100)
Subject: replace operator * with rv_mul
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ea2e7b35b4f40f670eeabd17a27de3a39b283fe5;p=riscv-isa-sim.git

replace operator * with rv_mul
---

diff --git a/riscv/insns/mul.h b/riscv/insns/mul.h
index 0102d36..d91ab08 100644
--- a/riscv/insns/mul.h
+++ b/riscv/insns/mul.h
@@ -1,2 +1,2 @@
 require_extension('M');
-WRITE_RD(sext_xlen(RS1 * RS2));
+WRITE_RD(sext_xlen(rv_mul(RS1, RS2)));
diff --git a/riscv/insns/mulh.h b/riscv/insns/mulh.h
index 051382a..737b9cb 100644
--- a/riscv/insns/mulh.h
+++ b/riscv/insns/mulh.h
@@ -2,4 +2,4 @@ require_extension('M');
 if (xlen == 64)
   WRITE_RD(mulh(RS1, RS2));
 else
-  WRITE_RD(sext32((sext32(RS1) * sext32(RS2)) >> 32));
+  WRITE_RD(sext32((rv_mul(sext32(RS1), sext32(RS2))) >> 32));
diff --git a/riscv/insns/mulhsu.h b/riscv/insns/mulhsu.h
index c53f90b..6890799 100644
--- a/riscv/insns/mulhsu.h
+++ b/riscv/insns/mulhsu.h
@@ -2,4 +2,4 @@ require_extension('M');
 if (xlen == 64)
   WRITE_RD(mulhsu(RS1, RS2));
 else
-  WRITE_RD(sext32((sext32(RS1) * reg_t((uint32_t)RS2)) >> 32));
+  WRITE_RD(sext32((rv_mul(sext32(RS1), reg_t((uint32_t)RS2))) >> 32));
diff --git a/riscv/insns/mulhu.h b/riscv/insns/mulhu.h
index 1ae3650..a9527b2 100644
--- a/riscv/insns/mulhu.h
+++ b/riscv/insns/mulhu.h
@@ -2,4 +2,5 @@ require_extension('M');
 if (xlen == 64)
   WRITE_RD(mulhu(RS1, RS2));
 else
-  WRITE_RD(sext32(((uint64_t)(uint32_t)RS1 * (uint64_t)(uint32_t)RS2) >> 32));
+  WRITE_RD(sext32((rv_mul((uint64_t)(uint32_t)RS1,
+                          (uint64_t)(uint32_t)RS2)) >> 32));
diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 603defe..e5be643 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -237,3 +237,8 @@ reg_t sv_proc_t::rv_div(reg_t lhs, reg_t rhs)
     return lhs / rhs;
 }
 
+reg_t sv_proc_t::rv_mul(reg_t lhs, reg_t rhs)
+{
+    return lhs * rhs;
+}
+
diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index 6a029bb..7112dd5 100644
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -98,6 +98,7 @@ public:
     reg_t rv_sub(reg_t lhs, reg_t rhs);
     reg_t rv_div(reg_t lhs, reg_t rhs);
     sreg_t rv_div(sreg_t lhs, sreg_t rhs);
+    reg_t rv_mul(reg_t lhs, reg_t rhs);
 
 #include "sv_insn_decl.h"
 };