From: lkcl <lkcl@web>
Date: Sun, 3 May 2020 13:20:43 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~2769
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ea306d058e0bc62ce8debd22b83a74df45178f6e;p=libreriscv.git

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diff --git a/3d_gpu/architecture/regfile.mdwn b/3d_gpu/architecture/regfile.mdwn
new file mode 100644
index 000000000..cd735fc3b
--- /dev/null
+++ b/3d_gpu/architecture/regfile.mdwn
@@ -0,0 +1,14 @@
+# Register Files
+
+A minimum of 3 register files are required for POWER:
+
+* Floating-point
+* Integer
+* Control and Condition Code Registers (CR0-7, CTR, LR)
+* SPRs (Special Purpose Registers)
+
+The FP and Integer registers need to be a massive 128 x 64-bit.
+
+# Connectivity between regfiles and Function Units
+
+[[!img regfile_hilo_32_odd_even.reg]]