From: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Date: Tue, 23 Jul 2019 09:52:36 +0000 (+0200)
Subject: radv/gfx10: fix VS input VGPRs with the legacy path
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ea337c8b7e9e987e7415f56e30f5707976b78e74;p=mesa.git

radv/gfx10: fix VS input VGPRs with the legacy path

For some reasons, InstanceID is VGPR3 although StepRate0 is set to 1.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
---

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index 336bae28614..cf73cdc692b 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -852,9 +852,15 @@ declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
 			}
 		} else {
 			if (ctx->ac.chip_class >= GFX10) {
-				add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* user vgpr */
-				add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* user vgpr */
-				add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
+				if (ctx->options->key.vs_common_out.as_ngg) {
+					add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* user vgpr */
+					add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* user vgpr */
+					add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
+				} else {
+					add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
+					add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
+					add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
+				}
 			} else {
 				add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
 				add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 736388c555c..5fd1022b05a 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -765,7 +765,7 @@ static void radv_postprocess_config(const struct radv_physical_device *pdevice,
 			if (info->vs.export_prim_id) {
 				vgpr_comp_cnt = 2;
 			} else if (info->info.vs.needs_instance_id) {
-				vgpr_comp_cnt = 1;
+				vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
 			} else {
 				vgpr_comp_cnt = 0;
 			}
@@ -837,7 +837,11 @@ static void radv_postprocess_config(const struct radv_physical_device *pdevice,
 
 		if (es_type == MESA_SHADER_VERTEX) {
 			/* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
-			es_vgpr_comp_cnt = info->info.vs.needs_instance_id ? 1 : 0;
+			if (info->info.vs.needs_instance_id) {
+				es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
+			} else {
+				es_vgpr_comp_cnt = 0;
+			}
 		} else if (es_type == MESA_SHADER_TESS_EVAL) {
 			es_vgpr_comp_cnt = info->info.uses_prim_id ? 3 : 2;
 		} else {