From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 8 Apr 2022 22:49:37 +0000 (-0700)
Subject: clean up EqualLeadingZeroCount.elaborate
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ea368079151a9844c93691df3a7256c55cc22e8b;p=nmigen-gf.git

clean up EqualLeadingZeroCount.elaborate
---

diff --git a/src/nmigen_gf/hdl/cldivrem.py b/src/nmigen_gf/hdl/cldivrem.py
index 77c4b14..f6ca4e8 100644
--- a/src/nmigen_gf/hdl/cldivrem.py
+++ b/src/nmigen_gf/hdl/cldivrem.py
@@ -77,16 +77,18 @@ class EqualLeadingZeroCount(Elaboratable):
         both_ones = Signal(self.width)
         different = Signal(self.width)
 
-        # build both_ones and different such that:
-        # * if both_ones is set, then both_ones[i] and different[i] are both
-        #   ones in order to set the carry bit out.
-        # * if different is set, then both_ones[i] and different[i] are both
-        #   zeros in order to clear the carry bit out.
-        # * otherwise exactly one of both_ones[i] and different[i] are set and
+        # build `both_ones` and `different` such that:
+        # for every bit index `i`:
+        # * if `both_ones[i]` is set, then both addends bits at index `i` are
+        #   set in order to set the carry bit out, since `cin + 1 + 1` always
+        #   has a carry out.
+        # * if `different[i]` is set, then both addends bits at index `i` are
+        #   zeros in order to clear the carry bit out, since `cin + 0 + 0`
+        #   never has a carry out.
+        # * otherwise exactly one of the addends bits at index `i` is set and
         #   the other is clear in order to propagate the carry bit from
-        #   less significant bits.
-        # * different is zero when both_ones is set, so we don't need to
-        #   OR-in both_ones
+        #   less significant bits, since `cin + 1 + 0` has a carry out that is
+        #   equal to `cin`.
 
         # `both_ones` is set if both have no leading zeros so far
         m.d.comb += both_ones.eq(self.a & self.b)
@@ -96,7 +98,7 @@ class EqualLeadingZeroCount(Elaboratable):
 
         # now [ab]use add: the last bit [carry-out] is the result
         csum = Signal(self.width + 1)
-        carry_in = 1  # both have no leading zeros so far, so set carry
+        carry_in = 1  # both have no leading zeros so far, so set carry in
         m.d.comb += csum.eq(both_ones + (~different) + carry_in)
         m.d.comb += self.out.eq(csum[self.width])  # out is carry-out