From: Gabe Black <gabeblack@google.com>
Date: Tue, 13 Mar 2018 00:41:15 +0000 (-0700)
Subject: x86: Implement the RDTSCP instruction.
X-Git-Tag: v19.0.0.0~2233
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ea383880c61023360aee672c6197f2cda9889f07;p=gem5.git

x86: Implement the RDTSCP instruction.

This is very similar to RDTSC, except that it requires all younger
instructions to retire before it completes, and it writes the TSC_AUX
MSR into ECX. I've added an mfence as an iniitial microop to ensure
that memory accesses complete before RDTSCP runs, and added an rdval
microop at the end to read the TSC_AUX value into ECX.

Change-Id: I9766af562b7fd0c22e331b56e06e8818a9e268c9
Reviewed-on: https://gem5-review.googlesource.com/9043
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
---

diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index aa60e4c48..761e8381e 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -133,7 +133,7 @@
                 0x7: decode MODRM_MOD {
                     0x3: decode MODRM_RM {
                         0x0: Inst::SWAPGS();
-                        0x1: rdtscp();
+                        0x1: Inst::RDTSCP();
                         default: Inst::UD2();
                     }
                     default: Inst::INVLPG(M);
diff --git a/src/arch/x86/isa/insts/system/msrs.py b/src/arch/x86/isa/insts/system/msrs.py
index fe9c5b262..b79b6dbe9 100644
--- a/src/arch/x86/isa/insts/system/msrs.py
+++ b/src/arch/x86/isa/insts/system/msrs.py
@@ -66,4 +66,15 @@ def macroop RDTSC
     srli t1, t1, 32, dataSize=8
     mov rdx, rdx, t1, dataSize=4
 };
+
+def macroop RDTSCP
+{
+    .serialize_before
+    mfence
+    rdtsc t1
+    mov rax, rax, t1, dataSize=4
+    srli t1, t1, 32, dataSize=8
+    mov rdx, rdx, t1, dataSize=4
+    rdval rcx, "InstRegIndex(MISCREG_TSC_AUX)", dataSize=4
+};
 '''