From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 21 Jul 2018 10:49:50 +0000 (+0100)
Subject: add wb-axi converter
X-Git-Tag: convert-csv-opcode-to-binary~5038
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ea40cb5f22cbcf88ce152fa5d162e7e4746b8f7e;p=libreriscv.git

add wb-axi converter
---

diff --git a/shakti/m_class/wishbone.mdwn b/shakti/m_class/wishbone.mdwn
index 2434f3ef6..0b269e519 100644
--- a/shakti/m_class/wishbone.mdwn
+++ b/shakti/m_class/wishbone.mdwn
@@ -5,3 +5,4 @@ See also [[AXI]] Bus
 * <http://bugs.libre-riscv.org/show_bug.cgi?id=11>
 * <https://github.com/alexforencich/verilog-wishbone>
 * <https://github.com/qermit/WishboneAXI>
+* <https://github.com/bluecmd/wb-axi>