From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 20 Apr 2021 16:10:39 +0000 (+0100)
Subject: add enable MMU option to issuer_verilog.py
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ea52af4808c73d1f09eb44bc9256df02e9128a95;p=soc.git

add enable MMU option to issuer_verilog.py
---

diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py
index d2a0e546..a33801b0 100644
--- a/src/soc/fu/compunits/compunits.py
+++ b/src/soc/fu/compunits/compunits.py
@@ -274,9 +274,9 @@ class AllFunctionUnits(Elaboratable):
         if microwatt_mmu:
             print("cut here ==============================")
             alu = self.fus["mmu0"].alu
-            print("alu",alu)
+            print("alu", alu)
             pi = alu.pi
-            print("pi",pi)
+            print("pi", pi)
             pilist = [pi]
         if pilist is None:
             return
diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 446b7f41..3632d0e6 100644
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -32,6 +32,12 @@ if __name__ == '__main__':
     parser.add_argument("--disable-core", dest='core', action="store_false",
                         help="disable main core",
                         default=False)
+    parser.add_argument("--enable-mmu", dest='mmu', action="store_true",
+                        help="Enable mmu",
+                        default=False)
+    parser.add_argument("--disable-mmu", dest='mmu', action="store_false",
+                        help="Disable mmu",
+                        default=False)
     parser.add_argument("--enable-pll", dest='pll', action="store_true",
                         help="Enable pll",
                         default=False)
@@ -65,6 +71,8 @@ if __name__ == '__main__':
              'mul': 1,
              'shiftrot': 1
             }
+    if args.mmu:
+        units['mmu'] = 1 # enable MMU
 
     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
                          imem_ifacetype='bare_wb',
@@ -84,8 +92,10 @@ if __name__ == '__main__':
                          sram4x4kblock=args.enable_sram4x4kblock, # add SRAMs
                          debug=args.debug,      # set to jtag or dmi
                          svp64=args.svp64,      # enable SVP64
+                         mmu=args.mmu,          # enable MMU
                          units=units)
 
+    print("mmu", pspec.__dict__["mmu"])
     print("nocore", pspec.__dict__["nocore"])
     print("regreduce", pspec.__dict__["regreduce"])
     print("gpio", pspec.__dict__["gpio"])