From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 27 Jan 2020 11:12:53 +0000 (+0100)
Subject: README: update copyright year and make sure LICENSE/README both mention MiSoC
X-Git-Tag: 24jan2021_ls180~710
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ea5ef8c1be9f3a39fc2f030b0251c31f76c2dbf8;p=litex.git

README: update copyright year and make sure LICENSE/README both mention MiSoC
---

diff --git a/LICENSE b/LICENSE
index 8737a9ce..eb528fc7 100644
--- a/LICENSE
+++ b/LICENSE
@@ -1,6 +1,10 @@
-LiteX is a MiSoC-based SoC builder using Migen as Python DSL.
+LiteX is a FPGA design/SoC builder that can be used to build cores, create
+SoCs and full FPGA designs.
 
-Unless otherwise noted, LiteX is copyright (C) 2012-2019 Enjoy-Digital.
+LiteX is based on Migen/MiSoC and provides specific building/debugging tools
+for a higher level of abstraction and compatibily with the LiteX core ecosystem.
+
+Unless otherwise noted, LiteX is copyright (C) 2012-2020 Enjoy-Digital.
 Unless otherwise noted, MiSoC is copyright (C) 2012-2015 Enjoy-Digital.
 Unless otherwise noted, MiSoC is copyright (C) 2007-2015 M-Labs Ltd.
 All rights reserved.
diff --git a/README.md b/README.md
index d06b2687..8bb0a405 100644
--- a/README.md
+++ b/README.md
@@ -1,6 +1,6 @@
 ![LiteX](https://raw.githubusercontent.com/enjoy-digital/litex/master/doc/litex.png)
 ```
-              Copyright 2012-2019 / EnjoyDigital
+              Copyright 2012-2020 / EnjoyDigital
 ```
 [![](https://travis-ci.com/enjoy-digital/litex.svg?branch=master)](https://travis-ci.com/enjoy-digital/litex)
 ![License](https://img.shields.io/badge/License-BSD%202--Clause-orange.svg)
@@ -8,8 +8,8 @@
 LiteX is a FPGA design/SoC builder that can be used to build cores, create
 SoCs and full FPGA designs.
 
-LiteX is based on Migen and provides specific building/debugging tools for
-a higher level of abstraction and compatibily with the LiteX core ecosystem.
+LiteX is based on Migen/MiSoC and provides specific building/debugging tools
+for a higher level of abstraction and compatibily with the LiteX core ecosystem.
 
 Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a
 SoC builder to create/develop/debug FPGA SoCs in Python.
diff --git a/litex/soc/software/bios/main.c b/litex/soc/software/bios/main.c
index 621d377a..1133b036 100644
--- a/litex/soc/software/bios/main.c
+++ b/litex/soc/software/bios/main.c
@@ -567,7 +567,7 @@ int main(int i, char **c)
 	printf("\e[1m      / /__/ / __/ -_)>  <\e[0m\n");
 	printf("\e[1m     /____/_/\\__/\\__/_/|_|\e[0m\n");
 	printf("\n");
-	printf(" (c) Copyright 2012-2019 Enjoy-Digital\n");
+	printf(" (c) Copyright 2012-2020 Enjoy-Digital\n");
 	printf("\n");
 	printf(" BIOS built on "__DATE__" "__TIME__"\n");
 	crcbios();