From: Florent Kermarrec Date: Sat, 21 Feb 2015 22:33:49 +0000 (+0100) Subject: doc: remove IP X-Git-Tag: 24jan2021_ls180~2572^2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ea7962da120986156c589173b81acab5942f5a6f;p=litex.git doc: remove IP --- diff --git a/README b/README index b849cefe..8faed188 100644 --- a/README +++ b/README @@ -18,7 +18,7 @@ PDF : www.enjoy-digital.fr/litex/litesata.pdf LiteSATA provides a small footprint and configurable SATA gen1/2/3 core. LiteSATA is part of LiteX libraries whose aims are to lower entry level of complex -FPGA IP cores by providing simple, elegant and efficient implementations of +FPGA cores by providing simple, elegant and efficient implementations of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller... The core uses simple and specific streaming buses and will provides in the future diff --git a/doc/source/docs/intro/about.rst b/doc/source/docs/intro/about.rst index e27d930c..83865868 100644 --- a/doc/source/docs/intro/about.rst +++ b/doc/source/docs/intro/about.rst @@ -7,7 +7,7 @@ About LiteSATA LiteSATA provides a small footprint and configurable SATA gen1/2/3 core. LiteSATA is part of LiteX libraries whose aims is to lower entry level of complex -FPGA IP cores by providing simple, elegant and efficient implementations of +FPGA cores by providing simple, elegant and efficient implementations of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller... The core uses simple and specific streaming buses and will provides in the future