From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 4 Jul 2020 18:18:05 +0000 (+0100)
Subject: update trap docstring
X-Git-Tag: div_pipeline~162^2~84
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ea81c79b43ad750ddb84fc4a0ea95e16de0ddb68;p=soc.git

update trap docstring
---

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 662ff44c..0ba10012 100644
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -60,7 +60,8 @@ class TrapMainStage(PipeModBase):
         self.fields.create_specs()
 
     def trap(self, m, trap_addr, return_addr):
-        """trap """ # TODO add descriptive docstring
+        """trap.  sets new PC, stores MSR and old PC in SRR1 and SRR0
+        """
         comb  = m.d.comb
         msr_i = self.i.msr
         nia_o, srr0_o, srr1_o = self.o.nia, self.o.srr0, self.o.srr1