From: lkcl <lkcl@web>
Date: Wed, 25 May 2022 10:59:40 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2103
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ea838d024cc374bc1102f13234048b6313043a9b;p=libreriscv.git

---

diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn
index d16fe47e8..e83997d2c 100644
--- a/openpower/sv/int_fp_mv.mdwn
+++ b/openpower/sv/int_fp_mv.mdwn
@@ -79,6 +79,55 @@ work on *both* Fixed *and* Floating Point operands and results.
  The interactions with SVP64
 are explained in the  [[int_fp_mv/appendix]]
 
+# Float load immediate <a name="fmvis"></a>
+
+This is like a variant of `fmvfg`
+
+`fmvis FRT, FI`
+
+Reinterprets `FI << 16` as a 32-bit float, which is then converted to a
+64-bit float and written to `FRT`.  This is equivalent to reinterpreting
+`FI` as a `BF16` and converting to 64-bit float.
+
+There is no need for an Rc=1 variant because this is an immediate loading
+instruction. This frees up one extra bit in the X-Form format for packing
+a full `BF16`.
+
+Example:
+
+```
+# clearing a FPR
+fmvis f4, 0 # writes +0.0 to f4
+# loading handy constants
+fmvis f4, 0x8000 # writes -0.0 to f4
+fmvis f4, 0x3F80 # writes +1.0 to f4
+fmvis f4, 0xBF80 # writes -1.0 to f4
+fmvis f4, 0xBFC0 # writes -1.5 to f4
+fmvis f4, 0x7FC0 # writes +qNaN to f4
+fmvis f4, 0x7F80 # writes +Infinity to f4
+fmvis f4, 0xFF80 # writes -Infinity to f4
+fmvis f4, 0x3FFF # writes +1.9921875 to f4
+
+# clearing 128 FPRs with 2 SVP64 instructions
+# by issuing 32 vec4 (subvector length 4) ops
+setvli VL=MVL=32
+sv.fmvis/vec4 f0, 0 # writes +0.0 to f0-f127
+```
+Important: If the float load immediate instruction(s) are left out,
+change all [GPR to FPR conversion instructions](#GPR-to-FPR-conversions)
+to instead write `+0.0` if `RA` is register `0`, at least
+allowing clearing FPRs.
+
+`fmvis` fits well with DX-Form:
+
+|  0-5   | 6-10 | 11-15 | 16-25 | 26-30 | 31  | Form |
+|--------|------|-------|-------|-------|-----|-----|
+|  Major | FRT  | d1    | d0    | XO    | d2  | DX-Form |
+
+    bf16 = d0 || d1 || d2
+    fp32 = bf16 || [0]*16
+    FRT = Single_to_Double(fp32)
+
 # FPR to GPR moves
 
 * `fmvtg RT, FRA`
@@ -130,55 +179,6 @@ FPRF is set to the class and sign of the result, except for Invalid Operation Ex
       FX OX UX XX VXSNAN
       CR1 (if Rc=1)
 
-# Float load immediate <a name="fmvis"></a>
-
-This is like a variant of `fmvfg`
-
-`fmvis FRT, FI`
-
-Reinterprets `FI << 16` as a 32-bit float, which is then converted to a
-64-bit float and written to `FRT`.  This is equivalent to reinterpreting
-`FI` as a `BF16` and converting to 64-bit float.
-
-There is no need for an Rc=1 variant because this is an immediate loading
-instruction. This frees up one extra bit in the X-Form format for packing
-a full `BF16`.
-
-Example:
-
-```
-# clearing a FPR
-fmvis f4, 0 # writes +0.0 to f4
-# loading handy constants
-fmvis f4, 0x8000 # writes -0.0 to f4
-fmvis f4, 0x3F80 # writes +1.0 to f4
-fmvis f4, 0xBF80 # writes -1.0 to f4
-fmvis f4, 0xBFC0 # writes -1.5 to f4
-fmvis f4, 0x7FC0 # writes +qNaN to f4
-fmvis f4, 0x7F80 # writes +Infinity to f4
-fmvis f4, 0xFF80 # writes -Infinity to f4
-fmvis f4, 0x3FFF # writes +1.9921875 to f4
-
-# clearing 128 FPRs with 2 SVP64 instructions
-# by issuing 32 vec4 (subvector length 4) ops
-setvli VL=MVL=32
-sv.fmvis/vec4 f0, 0 # writes +0.0 to f0-f127
-```
-Important: If the float load immediate instruction(s) are left out,
-change all [GPR to FPR conversion instructions](#GPR-to-FPR-conversions)
-to instead write `+0.0` if `RA` is register `0`, at least
-allowing clearing FPRs.
-
-`fmvis` fits well with DX-Form:
-
-|  0-5   | 6-10 | 11-15 | 16-25 | 26-30 | 31  | Form |
-|--------|------|-------|-------|-------|-----|-----|
-|  Major | FRT  | d1    | d0    | XO    | d2  | DX-Form |
-
-    bf16 = d0 || d1 || d2
-    fp32 = bf16 || [0]*16
-    FRT = Single_to_Double(fp32)
-
 # Conversions
 
 Unlike the move instructions