From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 28 Feb 2020 21:03:40 +0000 (+0100)
Subject: soc/cores/uart/UARTCrossover: reduce fifo_depth to 1.
X-Git-Tag: 24jan2021_ls180~620
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ea8563339f96f2145490a772510545ef20d97af8;p=litex.git

soc/cores/uart/UARTCrossover: reduce fifo_depth to 1.
---

diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py
index fc4ec27f..dd59143f 100644
--- a/litex/soc/cores/uart.py
+++ b/litex/soc/cores/uart.py
@@ -272,7 +272,7 @@ class UARTCrossover(UART):
     def __init__(self, **kwargs):
         assert kwargs.get("phy", None) == None
         UART.__init__(self, **kwargs)
-        self.submodules.xover = UART(tx_fifo_depth=2, rx_fifo_depth=2, rx_fifo_rx_we=True)
+        self.submodules.xover = UART(tx_fifo_depth=1, rx_fifo_depth=1, rx_fifo_rx_we=True)
         self.comb += [
             self.source.connect(self.xover.sink),
             self.xover.source.connect(self.sink)