From: Eric Anholt <eric@anholt.net>
Date: Tue, 25 Feb 2014 20:15:31 +0000 (-0800)
Subject: i965: Switch mapping modes for non-explicit-flush blit-temporary maps.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ea93246c009178b54848a7814a172164cd33d3c7;p=mesa.git

i965: Switch mapping modes for non-explicit-flush blit-temporary maps.

On LLC, it should always be better to use a cached mapping than the GTT.
On non-LLC, it seems pretty silly to try to optimize read performance for
the INVALIDATE_RANGE_BIT case.  This will make the buffer_storage logic
easier.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
---

diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
index e6124dc1155..5bf453326aa 100644
--- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
@@ -421,11 +421,11 @@ intel_bufferobj_map_range(struct gl_context * ctx,
                                                              "range map",
                                                              length + extra,
                                                              alignment);
-	 if (!(access & GL_MAP_READ_BIT)) {
-	    drm_intel_gem_bo_map_gtt(intel_obj->range_map_bo[index]);
-	 } else {
+	 if (brw->has_llc) {
 	    drm_intel_bo_map(intel_obj->range_map_bo[index],
 			     (access & GL_MAP_WRITE_BIT) != 0);
+	 } else {
+	    drm_intel_gem_bo_map_gtt(intel_obj->range_map_bo[index]);
 	 }
 	 obj->Mappings[index].Pointer =
             intel_obj->range_map_bo[index]->virtual + extra;