From: lkcl <lkcl@web>
Date: Sun, 21 Aug 2022 17:33:42 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~798
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ea991619177aef1e60070293f4cf6d6dfd18c864;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 7b0187d1c..74b02f863 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -73,7 +73,7 @@ the main result.
 SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations:
 
 | 6 | 7 | 19-20 |  21 | 22   23 |  description     |
-| - | - | ----- | --- |---------|----------------- |
+| - | - |-------| --- |---------|----------------- |
 |sz |SNZ| 0 RG  |   0 | dz  /   | normal mode                      |
 |sz |SNZ| 0 RG  |   1 | 0   /   | scalar reduce mode (mapreduce), SUBVL=1 |
 |zz |SNZ| 0 RG  |   1 | 1   /   | parallel reduce mode (mapreduce), SUBVL=1 |