From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 5 Nov 2018 08:07:57 +0000 (+0000)
Subject: move csr reg and predicate table unpack to separate function
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eaa47adcd116029ed61b2810aa99d8b388c9aac5;p=riscv-isa-sim.git

move csr reg and predicate table unpack to separate function
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 622b829..ec8326f 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -397,6 +397,73 @@ int processor_t::paddr_bits()
   return max_xlen == 64 ? 50 : 34;
 }
 
+void state_t::sv_csr_reg_unpack()
+{
+    // okaaay and now "unpack" the CAM to make it easier to use.  this
+    // approach is not designed to be efficient right now.  optimise later
+    // first clear the old tables
+    memset(sv().sv_int_tb, 0, sizeof(sv().sv_int_tb));
+    memset(sv().sv_fp_tb, 0, sizeof(sv().sv_fp_tb));
+    // now walk the CAM and unpack it
+    for (int i = 0; i < sv_csr_sz(); i++)
+    {
+        union sv_reg_csr_entry *c = &sv().sv_csrs[i];
+        uint64_t idx = c->b.regkey;
+        sv_reg_entry *r;
+        if (c->u == 0)
+        {
+            break;
+        }
+        // XXX damn.  this basically duplicates sv_insn_t::get_regentry.
+        if (c->b.type == 1)
+        {
+            r = &sv().sv_int_tb[idx];
+        }
+        else
+        {
+            r = &sv().sv_fp_tb[idx];
+        }
+        r->elwidth = c->b.elwidth;
+        r->regidx = c->b.regidx;
+        r->isvec = c->b.isvec;
+        r->active = true;
+        fprintf(stderr, "setting REGCFG type:%d isvec:%d %d %d\n",
+                        c->b.type, r->isvec, (int)idx, (int)r->regidx);
+    }
+}
+
+void state_t::sv_csr_pred_unpack()
+{
+    memset(sv().sv_pred_int_tb, 0, sizeof(sv().sv_pred_int_tb));
+    memset(sv().sv_pred_fp_tb, 0, sizeof(sv().sv_pred_fp_tb));
+    for (int i = 0; i < sv_csr_sz(); i++)
+    {
+        union sv_pred_csr_entry *c = &sv().sv_pred_csrs[i];
+        uint64_t idx = c->b.regkey;
+        if (c->u == 0)
+        {
+            break;
+        }
+        sv_pred_entry *r;
+        // XXX damn.  this basically duplicates sv_insn_t::get_predentry.
+        if (c->b.type == 1)
+        {
+            r = &sv().sv_pred_int_tb[idx];
+        }
+        else
+        {
+            r = &sv().sv_pred_fp_tb[idx];
+        }
+        r->regidx = c->b.regidx;
+        r->zero   = c->b.zero;
+        r->inv    = c->b.inv;
+        r->packed = c->b.packed;
+        r->active = true;
+        fprintf(stderr, "setting PREDCFG %d type:%d zero:%d %d %d\n",
+                        i, c->b.type, r->zero, (int)idx, (int)r->regidx);
+    }
+}
+
 void processor_t::set_csr(int which, reg_t val)
 {
   val = _zext_xlen(val);
@@ -460,37 +527,7 @@ void processor_t::set_csr(int which, reg_t val)
           fprintf(stderr, "clr REGCFG %d\n", i);
           state.sv().sv_csrs[i].u = 0;
       }
-      // okaaay and now "unpack" the CAM to make it easier to use.  this
-      // approach is not designed to be efficient right now.  optimise later
-      // first clear the old tables
-      memset(state.sv().sv_int_tb, 0, sizeof(state.sv().sv_int_tb));
-      memset(state.sv().sv_fp_tb, 0, sizeof(state.sv().sv_fp_tb));
-      // now walk the CAM and unpack it
-      for (int i = 0; i < state.sv_csr_sz(); i++)
-      {
-        union sv_reg_csr_entry *c = &state.sv().sv_csrs[i];
-        uint64_t idx = c->b.regkey;
-        sv_reg_entry *r;
-        if (c->u == 0)
-        {
-            break;
-        }
-        // XXX damn.  this basically duplicates sv_insn_t::get_regentry.
-        if (c->b.type == 1)
-        {
-            r = &state.sv().sv_int_tb[idx];
-        }
-        else
-        {
-            r = &state.sv().sv_fp_tb[idx];
-        }
-        r->elwidth = c->b.elwidth;
-        r->regidx = c->b.regidx;
-        r->isvec = c->b.isvec;
-        r->active = true;
-        fprintf(stderr, "setting REGCFG type:%d isvec:%d %d %d\n",
-                        c->b.type, r->isvec, (int)idx, (int)r->regidx);
-      }
+      state.sv_csr_reg_unpack();
       break;
     }
     case CSR_SVPREDCFG0:
@@ -520,34 +557,7 @@ void processor_t::set_csr(int which, reg_t val)
       {
           state.sv().sv_pred_csrs[i].u = 0;
       }
-      memset(state.sv().sv_pred_int_tb, 0, sizeof(state.sv().sv_pred_int_tb));
-      memset(state.sv().sv_pred_fp_tb, 0, sizeof(state.sv().sv_pred_fp_tb));
-      for (int i = 0; i < state.sv_csr_sz(); i++)
-      {
-        union sv_pred_csr_entry *c = &state.sv().sv_pred_csrs[i];
-        uint64_t idx = c->b.regkey;
-        if (c->u == 0)
-        {
-            break;
-        }
-        sv_pred_entry *r;
-        // XXX damn.  this basically duplicates sv_insn_t::get_predentry.
-        if (c->b.type == 1)
-        {
-            r = &state.sv().sv_pred_int_tb[idx];
-        }
-        else
-        {
-            r = &state.sv().sv_pred_fp_tb[idx];
-        }
-        r->regidx = c->b.regidx;
-        r->zero   = c->b.zero;
-        r->inv    = c->b.inv;
-        r->packed = c->b.packed;
-        r->active = true;
-        fprintf(stderr, "setting PREDCFG %d type:%d zero:%d %d %d\n",
-                        i, c->b.type, r->zero, (int)idx, (int)r->regidx);
-      }
+      state.sv_csr_pred_unpack();
       break;
     }
     case CSR_UREMAP:
diff --git a/riscv/processor.h b/riscv/processor.h
index ee37e2c..1be234d 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -166,6 +166,9 @@ struct state_t
   sv_shape_t shape[3];
 
   sv_shape_t *get_shape(reg_t reg);
+  void sv_csr_reg_unpack();
+  void sv_csr_pred_unpack();
+
 
 #endif