From: lkcl <lkcl@web>
Date: Tue, 22 Dec 2020 19:40:23 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1029
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eab042d7421e00056d0c4f0abceaae833a99be7f;p=libreriscv.git

---

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index a7b539bad..c2f54e56c 100644
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -70,15 +70,16 @@ Example
             to_test = iregs[RA] & testmask & mask
             iregs[RT+i] = popcount(to_test)
 
-TODO: a Vector CR-based version of the same, due to CRs being used for predication.
+TODO: a Vector CR-based version of the same, due to CRs being used for predication. This would use the same testing mechanism as branch: BO[0:2]
+where bit 2 is inv, bits 0:1 select the bit of the CR.
 
-     def iotacr(RT, BA): 
+     def iotacr(RT, BA, BO): 
         mask = get_src_predicate()
         count = 0
         for i in range(VL):
             if mask & (1<<i) == 0: continue
             iregs[RT+i] = count
-            if test_CR_bit(CR[i+BA]):
+            if test_CR_bit(CR[i+BA], BO):
                  count += 1
 
 # Scalar