From: Eddie Hung Date: Tue, 27 Aug 2019 17:19:27 +0000 (-0700) Subject: Merge pull request #1292 from YosysHQ/mwk/xilinx_bufgmap X-Git-Tag: working-ls180~1097 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eab3c1432b717bb341773878bf0daece7d39dec8;p=yosys.git Merge pull request #1292 from YosysHQ/mwk/xilinx_bufgmap Add clock buffer insertion pass, improve iopadmap. --- eab3c1432b717bb341773878bf0daece7d39dec8