From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 7 Nov 2021 15:17:32 +0000 (+0000)
Subject: add quick test of regfiles to output rtlil
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eac26ec947cfd1d53e772217498e7851d0a00f4b;p=soc.git

add quick test of regfiles to output rtlil
---

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index 8f881423..469b891d 100644
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -31,6 +31,9 @@ from openpower.decoder.power_enums import SPRfull, SPRreduced
 # XXX MAKE DAMN SURE TO KEEP THESE UP-TO-DATE if changing/adding regs
 from openpower.consts import StateRegsEnum, XERRegsEnum, FastRegsEnum
 
+from nmigen import Module
+from nmigen.cli import rtlil
+
 
 # "State" Regfile
 class StateRegs(RegFileArray, StateRegsEnum):
@@ -206,3 +209,13 @@ class RegFiles:
             setattr(m.submodules, name, rf)
         return m
 
+if __name__ == '__main__':
+    m = Module()
+    from soc.config.test.test_loadstore import TestMemPspec
+    pspec = TestMemPspec()
+    rf = RegFiles(pspec)
+    rf.elaborate_into(m, None)
+    vl = rtlil.convert(m)
+    with open("test_regfiles.il", "w") as f:
+        f.write(vl)
+