From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sun, 11 Aug 2019 11:59:39 +0000 (+0200)
Subject: one bit enable signal
X-Git-Tag: working-ls180~1116^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ead2b52b5a123e2c93578555de394a7a406e1fa5;p=yosys.git

one bit enable signal
---

diff --git a/techlibs/efinix/brams_map.v b/techlibs/efinix/brams_map.v
index 3236f39a5..6786ae769 100644
--- a/techlibs/efinix/brams_map.v
+++ b/techlibs/efinix/brams_map.v
@@ -1,7 +1,7 @@
 module \$__EFINIX_5K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 	parameter CFG_ABITS = 8;
 	parameter CFG_DBITS = 20;
-	parameter CFG_ENABLE_A = 2;
+	parameter CFG_ENABLE_A = 1;
 
 	parameter CLKPOL2 = 1;
 	parameter CLKPOL3 = 1;