From: lkcl <lkcl@web>
Date: Tue, 19 Apr 2022 17:46:52 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2688
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eae511c02664512aaeee06624956fc149b8da7d0;p=libreriscv.git

---

diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn
index 63645c0e7..18cd7b0cd 100644
--- a/openpower/sv/biginteger.mdwn
+++ b/openpower/sv/biginteger.mdwn
@@ -41,7 +41,8 @@ ALU.
 
 ## Multiply
 
-Multiply is tricky: 64 bit operands actually produce a 128-bit result.
+Multiply is tricky: 64 bit operands actually produce a 128-bit result,
+which clearly cannot fit into an orthogonal register file.
 Most Scalar RISC ISAs have separate `mul-low-half` and `mul-hi-half`
 instructions, whilst some (OpenRISC) have "Accumulators" from which
 the results of the multiply must be explicitly extracted. High