From: Eddie Hung Date: Thu, 15 Aug 2019 21:51:12 +0000 (-0700) Subject: Use ID::keep more liberally too X-Git-Tag: working-ls180~1137^2~4 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eae5a6b12c0f44230f61ed23068e7200507f9520;p=yosys.git Use ID::keep more liberally too --- diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc index 97c88f423..c40c02acd 100644 --- a/passes/opt/muxpack.cc +++ b/passes/opt/muxpack.cc @@ -135,7 +135,7 @@ struct MuxpackWorker { for (auto wire : module->wires()) { - if (wire->port_output || wire->get_bool_attribute(ID(keep))) { + if (wire->port_output || wire->get_bool_attribute(ID::keep)) { for (auto bit : sigmap(wire)) sigbit_with_non_chain_users.insert(bit); } @@ -143,7 +143,7 @@ struct MuxpackWorker for (auto cell : module->cells()) { - if (cell->type.in(ID($mux), ID($pmux)) && !cell->get_bool_attribute(ID(keep))) + if (cell->type.in(ID($mux), ID($pmux)) && !cell->get_bool_attribute(ID::keep)) { SigSpec a_sig = sigmap(cell->getPort(ID::A)); SigSpec b_sig; diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index bf75c7adc..2f69b3d4c 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -52,7 +52,7 @@ struct keep_cache_t return cache.at(module); cache[module] = true; - if (!module->get_bool_attribute(ID(keep))) { + if (!module->get_bool_attribute(ID::keep)) { bool found_keep = false; for (auto cell : module->cells()) if (query(cell)) found_keep = true; @@ -122,7 +122,7 @@ void rmunused_module_cells(Module *module, bool verbose) for (auto &it : module->wires_) { Wire *wire = it.second; - if (wire->port_output || wire->get_bool_attribute(ID(keep))) { + if (wire->port_output || wire->get_bool_attribute(ID::keep)) { for (auto bit : sigmap(wire)) for (auto c : wire2driver[bit]) queue.insert(c), unused.erase(c); @@ -297,7 +297,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos if (!wire->port_input) used_signals_nodrivers.add(sig); } - if (wire->get_bool_attribute(ID(keep))) { + if (wire->get_bool_attribute(ID::keep)) { RTLIL::SigSpec sig = RTLIL::SigSpec(wire); assign_map.apply(sig); used_signals.add(sig); @@ -323,7 +323,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos if (wire->port_id == 0) goto delete_this_wire; } else - if (wire->port_id != 0 || wire->get_bool_attribute(ID(keep)) || !initval.is_fully_undef()) { + if (wire->port_id != 0 || wire->get_bool_attribute(ID::keep) || !initval.is_fully_undef()) { // do not delete anything with "keep" or module ports or initialized wires } else if (!purge_mode && check_public_name(wire->name) && (raw_used_signals.check_any(s1) || used_signals.check_any(s2) || s1 != s2)) { diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 85ec9a55a..f7469853b 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -61,7 +61,7 @@ void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) } if (wire->port_input) driven_signals.add(sigmap(wire)); - if (wire->port_output || wire->get_bool_attribute(ID(keep))) + if (wire->port_output || wire->get_bool_attribute(ID::keep)) used_signals.add(sigmap(wire)); all_signals.add(sigmap(wire)); } diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc index 733bc547c..c4f278706 100644 --- a/passes/opt/opt_lut.cc +++ b/passes/opt/opt_lut.cc @@ -104,7 +104,7 @@ struct OptLutWorker if (cell->has_keep_attr()) continue; SigBit lut_output = cell->getPort(ID::Y); - if (lut_output.wire->get_bool_attribute(ID(keep))) + if (lut_output.wire->get_bool_attribute(ID::keep)) continue; int lut_width = cell->getParam(ID(WIDTH)).as_int(); diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 3d7e9cccb..3c486bbcc 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -137,7 +137,7 @@ struct OptMuxtreeWorker } } for (auto wire : module->wires()) { - if (wire->port_output || wire->get_bool_attribute(ID(keep))) + if (wire->port_output || wire->get_bool_attribute(ID::keep)) for (int idx : sig2bits(RTLIL::SigSpec(wire))) bit2info[idx].seen_non_mux = true; } diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 792c69c55..37de8cb61 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -398,7 +398,7 @@ struct WreduceWorker SigMap init_attr_sigmap = mi.sigmap; for (auto w : module->wires()) { - if (w->get_bool_attribute(ID(keep))) + if (w->get_bool_attribute(ID::keep)) for (auto bit : mi.sigmap(w)) keep_bits.insert(bit); if (w->attributes.count(ID(init))) { diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 205f05ab9..4e49b73ba 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -198,7 +198,7 @@ void extract_cell(RTLIL::Cell *cell, bool keepff) if (keepff) for (auto &c : sig_q.chunks()) if (c.wire != NULL) - c.wire->attributes[ID(keep)] = 1; + c.wire->attributes[ID::keep] = 1; assign_map.apply(sig_d); assign_map.apply(sig_q); @@ -787,7 +787,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin extract_cell(c, keepff); for (auto &wire_it : module->wires_) { - if (wire_it.second->port_id > 0 || wire_it.second->get_bool_attribute(ID(keep))) + if (wire_it.second->port_id > 0 || wire_it.second->get_bool_attribute(ID::keep)) mark_port(RTLIL::SigSpec(wire_it.second)); } diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 898cb77a4..a2551316f 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -226,7 +226,7 @@ struct IopadmapPass : public Pass { cell->setPort(RTLIL::escape_id(tinoutpad_portname2), owire); cell->setPort(RTLIL::escape_id(tinoutpad_portname3), data_sig); cell->setPort(RTLIL::escape_id(tinoutpad_portname4), wire_bit); - cell->attributes[ID(keep)] = RTLIL::Const(1); + cell->attributes[ID::keep] = RTLIL::Const(1); for (auto cn : tbuf_cache.second) { auto c = module->cell(cn); @@ -263,7 +263,7 @@ struct IopadmapPass : public Pass { cell->setPort(RTLIL::escape_id(toutpad_portname), en_sig); cell->setPort(RTLIL::escape_id(toutpad_portname2), data_sig); cell->setPort(RTLIL::escape_id(toutpad_portname3), wire_bit); - cell->attributes[ID(keep)] = RTLIL::Const(1); + cell->attributes[ID::keep] = RTLIL::Const(1); for (auto cn : tbuf_cache.second) { auto c = module->cell(cn); @@ -390,7 +390,7 @@ struct IopadmapPass : public Pass { cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1); if (!nameparam.empty()) cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire->name), i)); - cell->attributes[ID(keep)] = RTLIL::Const(1); + cell->attributes[ID::keep] = RTLIL::Const(1); } } else @@ -403,7 +403,7 @@ struct IopadmapPass : public Pass { cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width); if (!nameparam.empty()) cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name)); - cell->attributes[ID(keep)] = RTLIL::Const(1); + cell->attributes[ID::keep] = RTLIL::Const(1); } wire->port_id = 0; diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index cb877c2f4..5e298d8dd 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -263,7 +263,7 @@ struct ShregmapWorker { for (auto wire : module->wires()) { - if (wire->port_output || wire->get_bool_attribute(ID(keep))) { + if (wire->port_output || wire->get_bool_attribute(ID::keep)) { for (auto bit : sigmap(wire)) { sigbit_with_non_chain_users.insert(bit); if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {}); @@ -283,7 +283,7 @@ struct ShregmapWorker for (auto cell : module->cells()) { - if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute(ID(keep))) + if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute(ID::keep)) { IdString d_port = opts.ffcells.at(cell->type).first; IdString q_port = opts.ffcells.at(cell->type).second; diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index fa038c1b9..b271c8781 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -145,7 +145,7 @@ struct TechmapWorker record.wire = it.second; record.value = it.second; result[p].push_back(record); - it.second->attributes[ID(keep)] = RTLIL::Const(1); + it.second->attributes[ID::keep] = RTLIL::Const(1); it.second->attributes[ID(_techmap_special_)] = RTLIL::Const(1); } }