From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 12 Jul 2020 10:46:22 +0000 (+0100)
Subject: missed setting of link register on OP_BC in PowerDecoder2
X-Git-Tag: div_pipeline~81
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eae68933f19cb2e6654eae215bd9256c896a523c;p=soc.git

missed setting of link register on OP_BC in PowerDecoder2
---

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 5ad8a89f..5f1e99ee 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -363,9 +363,11 @@ class DecodeOut2(Elaboratable):
             comb += self.reg_out.eq(self.dec.RA)
             comb += self.reg_out.ok.eq(1)
 
-        # BC or BCREG: potential implicit register (LR) output
+        # B, BC or BCREG: potential implicit register (LR) output
+        # these give bl, bcl, bclrl, etc.
         op = self.dec.op
         with m.If((op.internal_op == InternalOp.OP_BC) |
+                  (op.internal_op == InternalOp.OP_B) |
                   (op.internal_op == InternalOp.OP_BCREG)):
             with m.If(self.lk): # "link" mode
                 comb += self.fast_out.data.eq(FastRegs.LR) # constant: LR