From: lkcl Date: Mon, 17 Apr 2023 12:20:08 +0000 (+0100) Subject: (no commit message) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eae7b5d09e514b4aaae7e31d5b8dd852915c70a9;p=libreriscv.git --- diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index 03372f171..edb8ecf10 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -164,7 +164,7 @@ The following schedule for srcstep and dststep will occur: | 0 | 0 | both mask[src=0] and mask[dst=0] are 1 | | 1 | 2 | sz=1 but dz=0: dst skips mask[1], src soes not | | 2 | 3 | mask[src=2] and mask[dst=3] are 1 | -| end | end | loop has ended because dst reached VL-1 | +| 3 | end | loop has ended because dst reached VL-1 | Example 2: @@ -179,7 +179,7 @@ The following schedule for srcstep and dststep will occur: | 0 | 0 | both mask[src=0] and mask[dst=0] are 1 | | 2 | 1 | sz=0 but dz=1: src skips mask[1], dst does not | | 3 | 2 | mask[src=3] and mask[dst=2] are 1 | -| end | end | loop has ended because src reached VL-1 | +| end | 3 | loop has ended because src reached VL-1 | In both these examples it is crucial to note that despite there being a single predicate mask, with sz and dz being different, srcstep and @@ -200,7 +200,7 @@ The following schedule for srcstep and dststep will occur: | 3 | 3 | mask[src=3] and mask[dst=3] are 1 | | end | end | loop has ended because src and dst reached VL-1 | -Here, both srcstep and dststep remain in lockstep because sz=dz=1 +Here, both srcstep and dststep remain in lockstep because sz=dz=0 ## Twin Predication