From: whitequark <whitequark@whitequark.org>
Date: Thu, 27 Aug 2020 16:34:48 +0000 (+0000)
Subject: manual: fix typo.
X-Git-Tag: working-ls180~294^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eae88df016cc2134ba822e2a85ab92b955349fbe;p=yosys.git

manual: fix typo.
---

diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex
index 61d628a9c..ed8b4cd49 100644
--- a/manual/CHAPTER_Overview.tex
+++ b/manual/CHAPTER_Overview.tex
@@ -92,7 +92,7 @@ in different stages of the synthesis.
 
 \section{The RTL Intermediate Language}
 
-All frontends, passes and backends in Yosys operate on a design in RTLIL} representation.
+All frontends, passes and backends in Yosys operate on a design in RTLIL representation.
 The only exception are the high-level frontends that use the AST representation as an intermediate step before generating RTLIL
 data.