From: Luke Kenneth Casson Leighton Date: Mon, 9 May 2022 14:24:29 +0000 (+0100) Subject: comments for setvl were the wrong bit-position X-Git-Tag: sv_maxu_works-initial~433 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eaed69bdb7dee0774a75d44a8c7dc8f516b5ddc3;p=openpower-isa.git comments for setvl were the wrong bit-position not the actual fields (whew) --- diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index 11994cf8..7cdaa4b5 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -199,9 +199,9 @@ class SVP64Asm: insn |= fields[0] << (31-10) # RT , bits 6-10 insn |= fields[1] << (31-15) # RA , bits 11-15 insn |= (fields[2]-1) << (31-22) # SVi , bits 16-22 - insn |= fields[3] << (31-25) # ms , bit 25 + insn |= fields[3] << (31-25) # vf , bit 25 insn |= fields[4] << (31-24) # vs , bit 24 - insn |= fields[5] << (31-23) # vf , bit 23 + insn |= fields[5] << (31-23) # ms , bit 23 insn |= 0b00000 << (31-30) # XO , bits 26..30 if opcode == 'setvl.': insn |= 1 << (31-31) # Rc=1 , bit 31