From: Matt Turner Date: Thu, 16 Jul 2020 06:05:30 +0000 (-0700) Subject: intel/tools: Test notification subregisters X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eaf27eb512c5ffdedf8106e006448c5aabdfe447;p=mesa.git intel/tools: Test notification subregisters Reviewed-by: Sagar Ghuge Part-of: --- diff --git a/src/intel/tools/tests/gen7.5/wait.asm b/src/intel/tools/tests/gen7.5/wait.asm index ea69c7e049d..f94845cd8a1 100644 --- a/src/intel/tools/tests/gen7.5/wait.asm +++ b/src/intel/tools/tests/gen7.5/wait.asm @@ -1 +1,3 @@ wait(1) n0<0>.xUD { align16 WE_all 1N }; +wait(1) n0<0>.yUD { align16 WE_all 1N }; +wait(1) n0<0>.zUD { align16 WE_all 1N }; diff --git a/src/intel/tools/tests/gen7.5/wait.expected b/src/intel/tools/tests/gen7.5/wait.expected index c227101e16e..036512e412f 100644 --- a/src/intel/tools/tests/gen7.5/wait.expected +++ b/src/intel/tools/tests/gen7.5/wait.expected @@ -1 +1,3 @@ 30 03 00 00 00 70 01 32 00 12 00 00 04 00 6e 00 +30 03 00 00 00 70 02 32 05 12 05 00 04 00 6e 00 +30 03 00 00 00 70 04 32 0a 12 0a 00 04 00 6e 00 diff --git a/src/intel/tools/tests/gen7/wait.asm b/src/intel/tools/tests/gen7/wait.asm index ea69c7e049d..f94845cd8a1 100644 --- a/src/intel/tools/tests/gen7/wait.asm +++ b/src/intel/tools/tests/gen7/wait.asm @@ -1 +1,3 @@ wait(1) n0<0>.xUD { align16 WE_all 1N }; +wait(1) n0<0>.yUD { align16 WE_all 1N }; +wait(1) n0<0>.zUD { align16 WE_all 1N }; diff --git a/src/intel/tools/tests/gen7/wait.expected b/src/intel/tools/tests/gen7/wait.expected index c227101e16e..036512e412f 100644 --- a/src/intel/tools/tests/gen7/wait.expected +++ b/src/intel/tools/tests/gen7/wait.expected @@ -1 +1,3 @@ 30 03 00 00 00 70 01 32 00 12 00 00 04 00 6e 00 +30 03 00 00 00 70 02 32 05 12 05 00 04 00 6e 00 +30 03 00 00 00 70 04 32 0a 12 0a 00 04 00 6e 00 diff --git a/src/intel/tools/tests/gen8/wait.asm b/src/intel/tools/tests/gen8/wait.asm index 0c8fbc3bef4..14c0b678e64 100644 --- a/src/intel/tools/tests/gen8/wait.asm +++ b/src/intel/tools/tests/gen8/wait.asm @@ -1 +1,3 @@ -wait(1) n0<0>UD { align1 WE_all 1N }; +wait(1) n0.0<0>UD { align1 WE_all 1N }; +wait(1) n0.1<0>UD { align1 WE_all 1N }; +wait(1) n0.2<0>UD { align1 WE_all 1N }; diff --git a/src/intel/tools/tests/gen8/wait.expected b/src/intel/tools/tests/gen8/wait.expected index 81603b02af6..31565e5049f 100644 --- a/src/intel/tools/tests/gen8/wait.expected +++ b/src/intel/tools/tests/gen8/wait.expected @@ -1 +1,3 @@ 30 00 00 00 04 00 00 32 00 12 00 38 00 00 8d 00 +30 00 00 00 04 00 04 32 04 12 00 38 00 00 8d 00 +30 00 00 00 04 00 08 32 08 12 00 38 00 00 8d 00 diff --git a/src/intel/tools/tests/gen9/wait.asm b/src/intel/tools/tests/gen9/wait.asm index 0c8fbc3bef4..14c0b678e64 100644 --- a/src/intel/tools/tests/gen9/wait.asm +++ b/src/intel/tools/tests/gen9/wait.asm @@ -1 +1,3 @@ -wait(1) n0<0>UD { align1 WE_all 1N }; +wait(1) n0.0<0>UD { align1 WE_all 1N }; +wait(1) n0.1<0>UD { align1 WE_all 1N }; +wait(1) n0.2<0>UD { align1 WE_all 1N }; diff --git a/src/intel/tools/tests/gen9/wait.expected b/src/intel/tools/tests/gen9/wait.expected index 81603b02af6..31565e5049f 100644 --- a/src/intel/tools/tests/gen9/wait.expected +++ b/src/intel/tools/tests/gen9/wait.expected @@ -1 +1,3 @@ 30 00 00 00 04 00 00 32 00 12 00 38 00 00 8d 00 +30 00 00 00 04 00 04 32 04 12 00 38 00 00 8d 00 +30 00 00 00 04 00 08 32 08 12 00 38 00 00 8d 00