From: Michael Nolan Date: Wed, 24 Jun 2020 18:20:49 +0000 (-0400) Subject: Update comments for LoadStoreUnitInterface X-Git-Tag: div_pipeline~281 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eaf68c563d3d22350db448cfd3fd7c9a15d56c40;p=soc.git Update comments for LoadStoreUnitInterface --- diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py index 74fee180..4e6f1986 100644 --- a/src/soc/minerva/units/loadstore.py +++ b/src/soc/minerva/units/loadstore.py @@ -22,9 +22,13 @@ class LoadStoreUnitInterface: self.x_store = Signal() # set to do a memory store self.x_store_data = Signal(data_wid) # The data to write when storing self.x_stall = Signal() # do nothing until low - self.x_valid = Signal() # Not entirely sure yet + self.x_valid = Signal() # Whether the x pipeline stage is + # currently enabled (I + # think?). Set to 1 for #now self.m_stall = Signal() # do nothing until low - self.m_valid = Signal() # Not entirely sure yet + self.m_valid = Signal() # Whether the m pipeline stage is + # currently enabled. Set + # to 1 for now # OUTPUTS self.x_busy = Signal() # set when the memory is busy