From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 13 Apr 2021 18:52:42 +0000 (+0000)
Subject: use METAL10 for topRoutingLayer
X-Git-Tag: LS180_RC3~119
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eaf9228c48c2939e0dbf9aebc197416973025423;p=soclayout.git

use METAL10 for topRoutingLayer
---

diff --git a/experiments10_verilog/freepdk_c4m45/doDesign.py b/experiments10_verilog/freepdk_c4m45/doDesign.py
index 2628842..613e7e3 100644
--- a/experiments10_verilog/freepdk_c4m45/doDesign.py
+++ b/experiments10_verilog/freepdk_c4m45/doDesign.py
@@ -77,7 +77,7 @@ def scriptMain ( **kw ):
         adderConf.cfg.anabatic.searchHalo = 2
         adderConf.cfg.anabatic.globalIterations = 20
         adderConf.cfg.anabatic.routingGauge = 'FlexLib'
-        adderConf.cfg.anabatic.topRoutingLayer = 'METAL5'
+        adderConf.cfg.anabatic.topRoutingLayer = 'METAL10'
         adderConf.cfg.block.spareSide = u(7*13)
         #adderConf.cfg.chip.padCoreSide = 'North'
         adderConf.cfg.chip.supplyRailWidth = u(35)