From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 1 Oct 2018 11:00:27 +0000 (+0100)
Subject: whoops vloop continuation logic the wrong way round
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eb0c1339c3339f51744e01e548a3091ff9c056fa;p=riscv-isa-sim.git

whoops vloop continuation logic the wrong way round

the loop has to continue if there is one vectorised register left
rather than stop if there is *no* vectorised registers
---

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index 92404e5..5da73bb 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -53,9 +53,9 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
 #endif
       if (vlen > 1)
       {
-        fprintf(stderr, "reg %s %x vloop %d vlen %d stop %d pred %lx\n",
+        fprintf(stderr, "reg %s %x vloop %d vlen %d stop %d pred %lx rd%lx\n",
                 xstr(INSN), INSNCODE, voffs, vlen, insn.stop_vloop(),
-                dest_pred & (1<<voffs));
+                dest_pred & (1<<voffs), READ_REG(insn._rd()));
       }
       insn.reset_caches(); // ready to increment offsets in next iteration
       if (insn.stop_vloop())
diff --git a/riscv/sv.cc b/riscv/sv.cc
index 1a16730..90ef354 100644
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -78,9 +78,9 @@ uint64_t sv_insn_t::remap(uint64_t reg, bool intreg, int &voffs, int &newoffs)
   // is not being "redirected", so just return the actual reg.
   if (!r->active)
   {
-    vloop_continue = false;
     return reg; // not active: return as-is
   }
+  vloop_continue = true;
 
   // next we go through the lookup table.  *THIS* is why the
   // sv_reg_entry table is 32 entries (5-bit) *NOT* 6 bits
@@ -92,9 +92,9 @@ uint64_t sv_insn_t::remap(uint64_t reg, bool intreg, int &voffs, int &newoffs)
   // we return the re-mapped register...
   if (!r->isvec) // scalar
   {
-    vloop_continue = false;
     return reg; 
   }
+  vloop_continue = true;
 
   // aaand now, as it's a "vector", FINALLY we can add on the loop-offset
   // which was passed in to the sv_insn_t constructor (by reference)
diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index 3999d06..5d2b2fc 100644
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -22,7 +22,7 @@ class sv_insn_t: public insn_t
 public:
   sv_insn_t(processor_t *pr, insn_bits_t bits, unsigned int f,
             uint64_t &p_rd, uint64_t &p_rs1, uint64_t &p_rs2, uint64_t &p_rs3) :
-            insn_t(bits), p(pr), vloop_continue(true), fimap(f),
+            insn_t(bits), p(pr), vloop_continue(false), fimap(f),
             cached_rd(0xff), cached_rs1(0xff),
             cached_rs2(0xff), cached_rs3(0xff),
             offs_rd(0), offs_rs1(0),
@@ -73,7 +73,7 @@ public:
   sv_pred_entry* get_predentry(uint64_t reg, bool isint);
   reg_t predicate(uint64_t reg, bool isint, bool &zeroing);
 
-  void reset_vloop_check(void) { vloop_continue = true; }
+  void reset_vloop_check(void) { vloop_continue = false; }
   bool stop_vloop(void) { return !vloop_continue; }
 
 private:
@@ -113,9 +113,9 @@ private:
     }
     else
     {
-        if (!sv_check_reg(isint, reg))
+        if (sv_check_reg(isint, reg))
         {
-            vloop_continue = false;
+            vloop_continue = true;
         }
     }
     return cached;