From: Tamar Christina <tamar.christina@arm.com>
Date: Wed, 7 Jun 2017 09:36:17 +0000 (+0000)
Subject: 2017-06-07  Tamar Christina  <tamar.christina@arm.com>
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eb1d2d5d99be1d98880da1da0697c290fb787640;p=gcc.git

2017-06-07  Tamar Christina  <tamar.christina@arm.com>

        * config/aarch64/aarch64.md
        (copysignsf3): Fix mask generation.

From-SVN: r248949
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f5fc52765d5..7eb35287626 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2017-06-07  Tamar Christina  <tamar.christina@arm.com>
+
+	* config/aarch64/aarch64.md
+	(copysignsf3): Fix mask generation.
+
 2017-06-07  Jakub Jelinek  <jakub@redhat.com>
 
 	* dumpfile.h (enum tree_dump_index): Rename TDI_generic to
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index d89df66fecc..2e9331fd72b 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -4973,14 +4973,16 @@
    (match_operand:SF 2 "register_operand")]
   "TARGET_FLOAT && TARGET_SIMD"
 {
-  rtx mask = gen_reg_rtx (DImode);
+  rtx v_bitmask = gen_reg_rtx (V2SImode);
 
   /* Juggle modes to get us in to a vector mode for BSL.  */
-  rtx op1 = lowpart_subreg (V2SFmode, operands[1], SFmode);
+  rtx op1 = lowpart_subreg (DImode, operands[1], SFmode);
   rtx op2 = lowpart_subreg (V2SFmode, operands[2], SFmode);
   rtx tmp = gen_reg_rtx (V2SFmode);
-  emit_move_insn (mask, GEN_INT (HOST_WIDE_INT_1U << 31));
-  emit_insn (gen_aarch64_simd_bslv2sf (tmp, mask, op2, op1));
+  emit_move_insn (v_bitmask,
+		  aarch64_simd_gen_const_vector_dup (V2SImode,
+						     HOST_WIDE_INT_M1U << 31));
+  emit_insn (gen_aarch64_simd_bslv2sf (tmp, v_bitmask, op2, op1));
   emit_move_insn (operands[0], lowpart_subreg (SFmode, tmp, V2SFmode));
   DONE;
 }