From: Stafford Horne Date: Wed, 12 Jun 2019 21:16:19 +0000 (+0900) Subject: cpu/or1k: Document no branch delay slot architectures and l.adrp X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eb212c84a12bd0adb29792737ab2423d72c182f7;p=binutils-gdb.git cpu/or1k: Document no branch delay slot architectures and l.adrp The 'nd' architectures did not mention what the 'nd' stands for. Document that these mean 'no brach delay slot'. cpu/ChangeLog: yyyy-mm-dd Stafford Horne * or1k.cpu (or64nd, or32nd, or1200nd): Update comment.a (l-adrp): Improve comment. --- diff --git a/cpu/ChangeLog b/cpu/ChangeLog index 7f141af8bad..087e6c67f3a 100644 --- a/cpu/ChangeLog +++ b/cpu/ChangeLog @@ -1,3 +1,8 @@ +2019-06-13 Stafford Horne + + * or1k.cpu (or64nd, or32nd, or1200nd): Update comment.a + (l-adrp): Improve comment. + 2019-06-13 Stafford Horne * or1korfpx.cpu (insn-opcode-float-regreg): Add SFUEQ_S, SFUNE_S, diff --git a/cpu/or1k.cpu b/cpu/or1k.cpu index e1ae1b8c886..b796862d1b5 100644 --- a/cpu/or1k.cpu +++ b/cpu/or1k.cpu @@ -77,7 +77,7 @@ (define-mach (name or32nd) - (comment "Generic OpenRISC 1000 32-bit CPU") + (comment "Generic OpenRISC 1000 32-bit CPU with no branch delay slot") (cpu or1k32bf) (bfd-name "or1knd") ) @@ -92,7 +92,7 @@ ; OpenRISC 1200 - 32-bit or1k CPU implementation (define-model - (name or1200nd) (comment "OpenRISC 1200 model") + (name or1200nd) (comment "OpenRISC 1200 model with no branch delay slot") (attrs NO-DELAY-SLOT) (mach or32nd) (unit u-exec "Execution Unit" () 1 1 () () () ()) @@ -120,7 +120,7 @@ (define-mach (name or64nd) - (comment "Generic OpenRISC 1000 ND 64-bit CPU") + (comment "Generic OpenRISC 1000 ND 64-bit CPU with no branch delay slot") (cpu or1k64bf) (bfd-name "or1k64nd") ) diff --git a/cpu/or1korbis.cpu b/cpu/or1korbis.cpu index 308f37861d4..3741d4c8f7d 100644 --- a/cpu/or1korbis.cpu +++ b/cpu/or1korbis.cpu @@ -433,7 +433,7 @@ ) ) -(dni l-adrp "adrp reg/disp21" +(dni l-adrp "load pc-relative page address" ((MACH ORBIS-MACHS)) "l.adrp $rD,${disp21}" (+ OPC_ADRP rD disp21)