From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 27 Nov 2018 02:40:34 +0000 (+0000)
Subject: split out cpu_mip to separate module
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eb38eb598b3695b055fcbe5cc78732c9130506a1;p=rv32.git

split out cpu_mip to separate module
---

diff --git a/cpu.py b/cpu.py
index 17172c9..7c8d2f3 100644
--- a/cpu.py
+++ b/cpu.py
@@ -83,28 +83,8 @@ class MIE:
 
 
 class MIP:
-    def __init__(self, comb, sync):
-        self.comb = comb
-        self.sync = sync
-        self.meip = Signal(name="mip_meip") # TODO: implement ext interrupts
-        self.seip = Signal(name="mip_seip")
-        self.ueip = Signal(name="mip_uiep")
-        self.mtip = Signal(name="mip_mtip") # TODO: implement timer interrupts
-        self.stip = Signal(name="mip_stip")
-        self.msip = Signal(name="mip_stip")
-        self.utip = Signal(name="mip_utip")
-        self.ssip = Signal(name="mip_ssip")
-        self.usip = Signal(name="mip_usip")
-
-        for n in dir(self):
-            if n in ['make', 'comb', 'sync'] or n.startswith("_"):
-                continue
-            self.comb += getattr(self, n).eq(0x0)
-
-    def make(self):
-        return Cat( self.usip, self.ssip, 0, self.msip,
-                    self.utip, self.stip, 0, self.mtip,
-                    self.ueip, self.seip, 0, self.meip, )
+    def __init__(self):
+        self.mip = Signal(32)
 
 
 class M:
@@ -446,7 +426,7 @@ class CPU(Module):
 
         # mip
         c[csr_mip  ] = [
-            csr_output_value.eq(mip.make()),
+            csr_output_value.eq(mip.mip),
             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
                                                   csr_written_value),
         ]
@@ -645,7 +625,12 @@ class CPU(Module):
         mstatus = MStatus(self.comb, self.sync)
         mie = MIE(self.comb, self.sync)
         misa = Misa(self.comb, self.sync)
-        mip = MIP(self.comb, self.sync)
+        mip = MIP()
+
+        mp = Instance("CPUMIP", name="cpu_mip",
+            o_mip = mip.mip)
+
+        self.specials += mp
 
         mii = Instance("CPUMIE", name="cpu_mie",
             o_mie = mie.mie,
diff --git a/cpu_mip.py b/cpu_mip.py
new file mode 100644
index 0000000..30a5cf3
--- /dev/null
+++ b/cpu_mip.py
@@ -0,0 +1,66 @@
+"""
+/*
+ * Copyright 2018 Jacob Lifshay
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ */
+`timescale 1ns / 1ps
+`include "riscv.vh"
+`include "cpu.vh"
+"""
+
+import string
+from migen import *
+from migen.fhdl import verilog
+from migen.fhdl.structure import _Operator
+
+from riscvdefs import *
+from cpudefs import *
+
+class CPUMIP(Module):
+    def __init__(self):
+        Module.__init__(self)
+        # TODO: implement ext interrupts
+        self.meip = Signal(name="mip_meip", reset=0)
+        self.seip = Signal(name="mip_seip", reset=0)
+        self.ueip = Signal(name="mip_uiep", reset=0)
+        # TODO: implement timer interrupts
+        self.mtip = Signal(name="mip_mtip", reset=0)
+        self.stip = Signal(name="mip_stip", reset=0)
+        self.msip = Signal(name="mip_stip", reset=0)
+        self.utip = Signal(name="mip_utip", reset=0)
+        self.ssip = Signal(name="mip_ssip", reset=0)
+        self.usip = Signal(name="mip_usip", reset=0)
+
+        self.mip = Signal(32)
+        self.comb += self.mip.eq(self.make())
+
+    def make(self):
+        return Cat( self.usip, self.ssip, 0, self.msip,
+                    self.utip, self.stip, 0, self.mtip,
+                    self.ueip, self.seip, 0, self.meip, )
+
+
+if __name__ == "__main__":
+    example = CPUMIP()
+    print(verilog.convert(example,
+         {
+           example.mip,
+           }))